Generic approach of putting BIOS tables at the end of memory
(in addition to their low locations) This adds the kontron 986LCD-M and the i945 as a sample. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
678d6140a5
commit
3c7f46b422
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@ -1,3 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) .... others
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* Copyright (C) 2008-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* 2006.1 yhlu add mptable cross 0x467 processing */
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@ -38,11 +57,32 @@ void move_gdt(unsigned long newgdt)
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printk_debug("ok\n");
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}
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#if HAVE_HIGH_TABLES == 1
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uint64_t high_tables_base = 0;
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uint64_t high_tables_size;
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#endif
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struct lb_memory *write_tables(void)
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{
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unsigned long low_table_start, low_table_end, new_low_table_end;
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unsigned long rom_table_start, rom_table_end;
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#if HAVE_HIGH_TABLES == 1
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/* Even if high tables are configured, all tables are copied both to the
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* low and the high area, so payloads and OSes don't need to know about
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* the high tables.
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*/
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unsigned long high_table_start, high_table_end=0;
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if (high_tables_base) {
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printk_debug("High Tables Base is %lx.\n", high_tables_base);
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high_table_start = high_tables_base;
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high_table_end = high_tables_base;
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} else {
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printk_debug("High Tables Base is not set.\n");
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}
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#endif
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rom_table_start = 0xf0000;
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rom_table_end = 0xf0000;
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/* Start low addr at 16 bytes instead of 0 because of a buglet
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@ -53,24 +93,47 @@ struct lb_memory *write_tables(void)
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post_code(0x9a);
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#if HAVE_LOW_TABLES == 1
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/* This table must be betweeen 0xf0000 & 0x100000 */
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rom_table_end = write_pirq_routing_table(rom_table_end);
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rom_table_end = (rom_table_end + 1023) & ~1023;
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#endif
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#if HAVE_HIGH_TABLES == 1
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if (high_tables_base) {
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high_table_end = write_pirq_routing_table(high_table_end);
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high_table_end = (high_table_end + 1023) & ~1023;
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}
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#endif
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/* Write ACPI tables */
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/* write them in the rom area because DSDT can be large (8K on epia-m) which
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* pushes coreboot table out of first 4K if set up in low table area
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*/
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#if HAVE_LOW_TABLES == 1
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rom_table_end = write_acpi_tables(rom_table_end);
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rom_table_end = (rom_table_end+1023) & ~1023;
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#endif
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#if HAVE_HIGH_TABLES == 1
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if (high_tables_base) {
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high_table_end = write_acpi_tables(high_table_end);
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high_table_end = (high_table_end+1023) & ~1023;
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}
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#endif
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/* copy the smp block to address 0 */
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post_code(0x96);
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/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
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#if HAVE_LOW_TABLES == 1
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new_low_table_end = write_smp_table(low_table_end); // low_table_end is 0x10 at this point
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#endif
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#if HAVE_HIGH_TABLES == 1
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if (high_tables_base) {
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high_table_end = write_smp_table(high_table_end);
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high_table_end = (high_table_end+1023) & ~1023;
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}
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#endif
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#if HAVE_MP_TABLE==1
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#if HAVE_MP_TABLE == 1
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/* Don't write anything in the traditional x86 BIOS data segment,
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* for example the linux kernel smp need to use 0x467 to pass reset vector
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* or use 0x40e/0x413 for EBDA finding...
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@ -104,8 +167,18 @@ struct lb_memory *write_tables(void)
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}
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// Relocate the GDT to reserved memory, so it won't get clobbered
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move_gdt(low_table_end);
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low_table_end += &gdt_end - &gdt;
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#if HAVE_HIGH_TABLES == 1
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if (high_tables_base) {
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move_gdt(high_table_end);
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high_table_end += &gdt_end - &gdt;
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high_table_end = (high_table_end+1023) & ~1023;
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} else {
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#endif
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move_gdt(low_table_end);
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low_table_end += &gdt_end - &gdt;
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#if HAVE_HIGH_TABLES == 1
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}
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#endif
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#if CONFIG_MULTIBOOT
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/* The Multiboot information structure */
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@ -119,5 +192,23 @@ struct lb_memory *write_tables(void)
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write_coreboot_table(low_table_start, low_table_end,
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rom_table_start, rom_table_end);
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#if 0 && HAVE_HIGH_TABLES == 1
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/* This is currently broken and should be severely refactored. Ideally
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* we only have a pointer to the coreboot table in the low memory, so
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* anyone can find the real position.
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* write_coreboot_table does a lot more than just writing the coreboot
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* table. It magically decides where the table should go, and therefore
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* it consumes two base addresses. If we call write_coreboot_table like
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* below, we get weird effects.
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*/
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/* And we want another copy in high area because the low area might be
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* corrupted
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*/
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if (high_tables_base) {
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write_coreboot_table(high_table_start, high_table_end,
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high_table_start, high_table_end);
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}
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#endif
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return get_lb_mem();
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}
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@ -1111,6 +1111,18 @@ define HAVE_MAINBOARD_RESOURCES
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comment "Enable if the mainboard/chipset requires extra entries in the memory map"
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end
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define HAVE_LOW_TABLES
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default 1
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export always
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comment "Enable if ACPI, PIRQ, MP tables are supposed to live in the low megabyte"
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end
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define HAVE_HIGH_TABLES
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default 0
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export always
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comment "Enable if ACPI, PIRQ, MP tables are supposed to live at top of memory"
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end
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define CONFIG_SPLASH_GRAPHIC
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default 0
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export used
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@ -3,6 +3,9 @@
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#include <boot/coreboot_tables.h>
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void lb_add_memory_range(struct lb_memory *mem,
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uint32_t type, uint64_t start, uint64_t size);
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struct lb_memory *write_tables(void);
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#endif /* BOOT_TABLES_H */
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@ -29,6 +29,8 @@ uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses HAVE_ACPI_TABLES
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uses HAVE_MAINBOARD_RESOURCES
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uses HAVE_HIGH_TABLES
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# SMP
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uses CONFIG_SMP
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uses CONFIG_LOGICAL_CPUS
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@ -160,6 +162,8 @@ default HAVE_MP_TABLE=1
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## Build code to provide ACPI support
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##
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default HAVE_ACPI_TABLES=1
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default HAVE_MAINBOARD_RESOURCES=1
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default HAVE_HIGH_TABLES=0
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##
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## Build code to export a CMOS option table
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@ -289,6 +289,11 @@ unsigned long write_acpi_tables(unsigned long start)
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printk_debug("ACPI: * DMI (Linux workaround)\n");
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memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
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#if HAVE_HIGH_TABLES == 1
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memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
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current += DMI_TABLE_SIZE;
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ALIGN_CURRENT;
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#endif
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printk_info("ACPI: done.\n");
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return current;
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@ -21,8 +21,30 @@
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#include <device/device.h>
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#include <console/console.h>
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#include <boot/tables.h>
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#include "chip.h"
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/* in arch/i386/boot/tables.c */
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extern uint64_t high_tables_base, high_tables_size;
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/* in northbridge/intel/i945/northbridge.c */
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extern uint64_t uma_memory_base, uma_memory_size;
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int add_mainboard_resources(struct lb_memory *mem)
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{
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#if HAVE_HIGH_TABLES == 1
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printk_debug("Adding high table area\n");
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lb_add_memory_range(mem, LB_MEM_TABLE,
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high_tables_base, high_tables_size);
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#endif
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printk_debug("Adding UMA memory area\n");
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lb_add_memory_range(mem, LB_MEM_RESERVED,
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uma_memory_base, uma_memory_size);
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return 0;
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("Kontron 986LCD-M Mainboard")
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};
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@ -93,12 +93,18 @@ static uint32_t find_pci_tolm(struct bus *bus)
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return tolm;
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}
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#if HAVE_HIGH_TABLES==1
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#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
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extern uint64_t high_tables_base, high_tables_size;
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#endif
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uint64_t uma_memory_base=0, uma_memory_size=0;
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static void pci_domain_set_resources(device_t dev)
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{
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uint32_t pci_tolm;
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uint8_t tolud, reg8;
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uint16_t reg16;
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unsigned long long tomk, tolmk;
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unsigned long long tomk;
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pci_tolm = find_pci_tolm(&dev->link[0]);
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@ -120,13 +126,13 @@ static void pci_domain_set_resources(device_t dev)
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switch (reg8) {
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case 0:
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tseg_size = 1024;
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break;
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break; /* TSEG = 1M */
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case 1:
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tseg_size = 2048;
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break;
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break; /* TSEG = 2M */
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case 2:
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tseg_size = 8192;
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break;
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break; /* TSEG = 8M */
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}
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printk_debug("%dM\n", tseg_size >> 10);
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@ -150,24 +156,32 @@ static void pci_domain_set_resources(device_t dev)
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printk_debug("%dM UMA\n", uma_size >> 10);
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tomk -= uma_size;
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/* For reserving UMA memory in the memory map */
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uma_memory_base = tomk * 1024ULL;
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uma_memory_size = uma_size * 1024ULL;
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}
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/* The following needs to be 2 lines, otherwise the second
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* number is always 0
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*/
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printk_info("Available memory: %dK", tomk);
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printk_info(" (%dM)\n", (tomk >> 10));
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tolmk = tomk;
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printk_info("Available memory: %dK", (uint32_t)tomk);
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printk_info(" (%dM)\n", (uint32_t)(tomk >> 10));
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/* Report the memory regions */
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ram_resource(dev, 3, 0, 640);
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ram_resource(dev, 4, 768, (tolmk - 768));
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ram_resource(dev, 4, 768, (tomk - 768));
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if (tomk > 4 * 1024 * 1024) {
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ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
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}
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assign_resources(&dev->link[0]);
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#if HAVE_HIGH_TABLES==1
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/* Leave some space for ACPI, PIRQ and MP tables */
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high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024;
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high_tables_size = HIGH_TABLES_SIZE * 1024;
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#endif
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}
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static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
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