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soc/intel/cannonlake: Add _DSM method for SD controller 

The SD controller seems to take some time after restarting
the clock at 1.8V before it actually switches from 3.3V to
1.8V. Add a _DSM method that simply sleeps when switching
between 3.3V and 1.8V. Otherwise, the kernel times out too
quickly waiting for the card to acknowledge the 1.8V switch.
The card itself is waiting until it sees the clk signal being
driven at 1.8V.

BUG=b:125441242
TEST=Boot Hatch with SD card and CR2 removed, observe voltage
switch succeeds.

Change-Id: I15090ed9f9bc90b35dfcba47c913e3d37b799d0b
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signef-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
V Sowmya 2019-03-19 19:55:14 +05:30 committed by Furquan Shaikh
parent 1044ebaa06
commit 3c8c81b1ac
1 changed files with 62 additions and 0 deletions
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62
src/soc/intel/cannonlake/acpi/scs.asl
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@ -84,6 +84,7 @@ Scope (\_SB.PCI0) {
Name (_ADR, 0x00140005)
Name (_DDN, "SD Controller")
Name (TEMP, 0)
Name (DSUU, ToUUID("f6c13ea5-65cd-461f-ab7a-29f7e8d5bd61"))
OperationRegion (SDPC, PCI_Config, 0x00, 0x100)
Field (SDPC, WordAcc, NoLock, Preserve)
@ -95,6 +96,67 @@ Scope (\_SB.PCI0) {
PGEN, 1, /* PG_ENABLE */
}
/* _DSM x86 Device Specific Method
* Arg0: UUID Unique function identifier
* Arg1: Integer Revision Level
* Arg2: Integer Function Index (0 = Return Supported Functions)
* Arg3: Package Parameters
*/
Method (_DSM, 4)
{
If (LEqual (Arg0, ^DSUU)) {
/* Check the revision */
If (LGreaterEqual (Arg1, Zero)) {
/* Switch statement based on the function index. */
Switch (ToInteger (Arg2)) {
/*
* Function Index 0 the return value is a buffer containing
* one bit for each function index, starting with zero.
* Bit 0 - Indicates whether there is support for any functions other than function 0.
* Bit 1 - Indicates support to clear power control register
* Bit 2 - Indicates support to set power control register
* Bit 3 - Indicates support to set 1.8V signalling
* Bit 4 - Indicates support to set 3.3V signalling
* Bit 5 - Indicates support for HS200 mode
* Bit 6 - Indicates support for HS400 mode
* Bit 9 - Indicates eMMC I/O Driver Strength
*/
/*
* For SD we have to support functions to
* set 1.8V signalling and 3.3V signalling [BIT4, BIT3]
*/
Case (0) {
Return (Buffer () { 0x19 })
}
/*
* Function Index 3: Set 1.8v signalling.
* We put a sleep of 100ms in this method to
* work around a known issue with detecting
* UHS SD card on PCH. This is to compensate
* for the SD VR slowness.
*/
Case (3) {
Sleep (100)
Return(Buffer () { 0x00 })
}
/*
* Function Index 4: Set 3.3v signalling.
* We put a sleep of 100ms in this method to
* work around a known issue with detecting
* UHS SD card on PCH. This is to compensate
* for the SD VR slowness.
*/
Case (4) {
Sleep (100)
Return(Buffer () { 0x00 })
}
}
}
}
Return(Buffer() { 0x0 })
}
Method(_INI)
{
/* Clear register 0x1C20/0x4820 */