diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 045dc89e4d..24cc907da7 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -109,6 +109,10 @@ chip soc/intel/tigerlake
 		[PchSerialIoIndexUART2] = PchSerialIoPci,
 	}"
 
+	# D3Hot and D3Cold for TCSS
+	register "TcssD3HotEnable" = "1"
+	register "TcssD3ColdEnable" = "1"
+
 	# TCSS USB3
 	register "TcssAuxOri" = "0"
 
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 83b6c0ae0c..eb6814e5bf 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -105,6 +105,10 @@ chip soc/intel/tigerlake
 		[PchSerialIoIndexUART2] = PchSerialIoPci,
 	}"
 
+	# D3Hot and D3Cold for TCSS
+	register "TcssD3HotEnable" = "1"
+	register "TcssD3ColdEnable" = "1"
+
 	# TCSS USB3
 	register "TcssAuxOri" = "0"