small cleanup attempt in sc520 code. there needs to be some major spring
cleaning git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2214 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
677267a82a
commit
3cb4dc9c6b
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@ -817,7 +817,7 @@ end
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define HT_CHAIN_UNITID_BASE
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default 1
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export always
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comment "this will be first hypertransport device's unitid base, if sb ht chain only has one ht device, it could be 0"
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comment "first hypertransport device's unitid base. if southbridge ht chain only has one ht device, it could be 0"
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end
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define HT_CHAIN_END_UNITID_BASE
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@ -56,69 +56,44 @@
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#define drcbendadr (( volatile unsigned long *)0xfffef018)
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#define eccctl (( volatile unsigned char *)0xfffef020)
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#define dbctl (( volatile unsigned char *)0xfffef040)
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void
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setupsc520(void){
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volatile unsigned char *cp;
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volatile unsigned short *sp;
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volatile unsigned long *edi;
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volatile unsigned long *par;
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/* do this to see if MMCR will start acting right.
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* we suspect you have to do SOMETHING to get things going.
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* I'm really starting to hate this processor.
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*/
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/* no, that did not help. I wonder what will?
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* outl(0x800df0cb, 0xfffc);
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*/
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/* well, this is special! You have to do SHORT writes to the locations,
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* even though they are CHAR in size and CHAR aligned and technically, a
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* SHORT write will result in -- yoo ha! -- over writing the next location!
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* Thanks to the u-boot guys for a reference code I can use.
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* with these short pointers, it now reliably comes up after power cycle
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* with printk. Ah yi yi.
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*/
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/* turn off the write buffer*/
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/* per the note above, make this a short? Let's try it.
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*/
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sp = (unsigned short *)0xfffef040;
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*sp = 0;
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// moved to auto.c by stepan
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setup_pars();
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#if 0
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/* as per the book: */
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/* PAR register setup */
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/* set up the PAR registers as they are on the MSM586SEG */
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par = (unsigned long *) 0xfffef088;
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void setupsc520(void)
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{
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volatile unsigned char *cp;
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volatile unsigned short *sp;
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volatile unsigned long *edi;
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/* do this to see if MMCR will start acting right. we suspect
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* you have to do SOMETHING to get things going. I'm really
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* starting to hate this processor.
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*/
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/* no, that did not help. I wonder what will?
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* outl(0x800df0cb, 0xfffc);
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*/
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/* well, this is special! You have to do SHORT writes to the
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* locations, even though they are CHAR in size and CHAR aligned
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* and technically, a SHORT write will result in -- yoo ha! --
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* over writing the next location! Thanks to the u-boot guys
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* for a reference code I can use. with these short pointers,
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* it now reliably comes up after power cycle with printk. Ah yi
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* yi.
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*/
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/* turn off the write buffer*/
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/* per the note above, make this a short? Let's try it. */
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sp = (unsigned short *)0xfffef040;
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*sp = 0;
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/* as per the book: */
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/* PAR register setup */
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/* set up the PAR registers as they are on the MSM586SEG */
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/* moved to auto.c by Stepan, Ron says: */
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/* NOTE: move this to mainboard.c ASAP */
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#if 1
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*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
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*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
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*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
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*par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
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*par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
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*par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
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*par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
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*par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
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*par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
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*par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
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*par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
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*par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
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*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
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*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
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*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
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#else
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par += 15;
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#endif
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*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
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#endif
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setup_pars();
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/* CPCSF register */
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sp = (unsigned short *)0xfffefc24;
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*sp = 0xfe;
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@ -178,12 +153,12 @@ setupsc520(void){
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outb(0x55, 0x80);
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#endif
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/*; set the uart baud rate clocks to the normal 1.8432 MHz.*/
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/* enable interrupts here? Why not? */
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/* set the uart baud rate clocks to the normal 1.8432 MHz.*/
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/* enable interrupts here? Why not? */
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cp = (unsigned char *)0xfffefcc0;
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*cp = 4 | 3; /* uart 1 clock source */
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*cp = 4 | 3; /* uart 1 clock source */
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cp = (unsigned char *)0xfffefcc4;
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*cp = 4; /* uart 2 clock source */
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*cp = 4; /* uart 2 clock source */
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#if 0
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/*; set the interrupt mapping registers.*/
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@ -204,20 +179,21 @@ setupsc520(void){
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cp = (unsigned char *)0x0fffefd51;
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*cp = 0x02;
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#endif
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/*; "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */
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#endif
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/* Stepan says: This needs to go to the msm586seg code */
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/* "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */
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outl(0xcf8, 0x08000683c);
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outl(0xcfc, 0xc); /* set the interrupt line */
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/*; Set the SC520 PCI host bridge to target mode to allow external*/
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/*; bus mastering events*/
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outl(0x0cf8,0x080000004); /*index the status command register on device 0*/
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outl(0xcfc, 0x2); /*set the memory access enable bit*/
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/* Set the SC520 PCI host bridge to target mode to
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* allow external bus mastering events
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*/
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/* index the status command register on device 0*/
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outl(0x0cf8,0x080000004);
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outl(0xcfc, 0x2); /*set the memory access enable bit*/
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OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
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}
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@ -632,9 +608,10 @@ bad_ram:
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/* This code is known to work on the digital logic board and on the technologic
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* systems ts5300
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*/
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int
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staticmem(void){
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volatile unsigned long *zero = (unsigned long *) CACHELINESZ;
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int staticmem(void)
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{
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volatile unsigned long *zero = (unsigned long *) CACHELINESZ;
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/* set up 0x18 .. **/
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*drcbendadr = 0x88;
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*drcmctl = 0x1e;
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@ -651,27 +628,27 @@ staticmem(void){
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/* two autorefreshes */
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*drcctl = 4;
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*zero = 0;
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print_err("one zero out on refresh\r\n");
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print_debug("one zero out on refresh\r\n");
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*zero = 0;
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print_err("two zero out on refresh\r\n");
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print_debug("two zero out on refresh\r\n");
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/* load mode register */
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*drcctl = 3;
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*zero = 0;
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print_err("DONE the load mode reg\r\n");
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print_debug("DONE the load mode reg\r\n");
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/* normal mode */
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*drcctl = 0x0;
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*zero = 0;
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print_err("DONE one last write and then turn on refresh etc\r\n");
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print_debug("DONE one last write and then turn on refresh etc\r\n");
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*drcctl = 0x18;
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*zero = 0;
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print_err("DONE the normal\r\n");
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print_debug("DONE the normal\r\n");
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*zero = 0xdeadbeef;
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if (*zero != 0xdeadbeef)
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print_err("NO LUCK\r\n");
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print_debug("NO LUCK\r\n");
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else
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print_err("did a store and load ...\r\n");
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print_debug("did a store and load ...\r\n");
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//print_err_hex32(*zero);
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// print_err(" zero is now "); print_err_hex32(*zero); print_err("\r\n");
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}
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@ -1,3 +1,7 @@
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/*
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* This file needs a major cleanup. Too much #if 0 code
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*/
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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@ -24,7 +28,8 @@ udelay(int microseconds) {
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sc520_udelay(microseconds);
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}
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/*
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* set up basic things ... PAR should NOT go here, as it might change with the mainboard.
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* set up basic things ...
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* PAR should NOT go here, as it might change with the mainboard.
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*/
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static void cpu_init(device_t dev)
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{
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@ -210,11 +215,18 @@ void sc520_enable_resources(device_t dev) {
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static struct device_operations pci_domain_ops = {
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.read_resources = pci_domain_read_resources,
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.set_resources = pci_domain_set_resources,
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.enable_resources = enable_resources,
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/*
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* If enable_resources is set to the generic enable_resources
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* function the whole thing will hang in an endless loop on
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* the ts5300. If this is really needed on another platform,
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* something is conceptionally wrong.
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*/
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.enable_resources = 0, //enable_resources,
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.init = 0,
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.scan_bus = pci_domain_scan_bus,
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};
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};
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#if 0
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static void cpu_bus_init(device_t dev)
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{
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printk_spew("cpu_bus_init\n");
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@ -231,6 +243,7 @@ static struct device_operations cpu_bus_ops = {
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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#endif
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static void enable_dev(struct device *dev)
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{
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@ -240,9 +253,14 @@ static void enable_dev(struct device *dev)
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dev->ops = &pci_domain_ops;
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pci_set_method(dev);
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}
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#if 0
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/* This is never hit as none of the sc520 boards have
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* an APIC cluster defined
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*/
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else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
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dev->ops = &cpu_bus_ops;
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}
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#endif
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}
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@ -4,11 +4,9 @@
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target technologic_ts5300
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mainboard technologic/ts5300
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option DEFAULT_CONSOLE_LOGLEVEL=10
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option MAXIMUM_CONSOLE_LOGLEVEL=10
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option DEFAULT_CONSOLE_LOGLEVEL=3
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option MAXIMUM_CONSOLE_LOGLEVEL=3
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option CONFIG_COMPRESS=1
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#option CONFIG_COMPRESS=0
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option CONFIG_CONSOLE_VGA=0
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#romimage "normal"
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@ -27,7 +25,8 @@ romimage "fallback"
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# option ROM_IMAGE_SIZE=48 * 1024 # 0x8000
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# option ROM_IMAGE_SIZE=64 * 1024 # 0x10000
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# option ROM_IMAGE_SIZE=512 * 1024 # 0x10000
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option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
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# option LINUXBIOS_EXTRA_VERSION=".0-Fallback"
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option LINUXBIOS_EXTRA_VERSION=".0"
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payload /home/stepan/filo-ts5300.elf
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end
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