soc/intel/broadwell: Separate PCH in devicetree

Flesh out the PCH configuration into a separate chip. Keep it within the
Broadwell SoC directory for now, to ease moving files around. The boards
were prepared beforehand and the devicetrees require next to no changes.

Tested on out-of-tree Acer Aspire E5-573, still boots.

Change-Id: I28d948f3e6d85e669d12b29516d867c1d1ae9e1a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46700
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/auron/devicetree.cb

@@ -26,7 +26,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end # vga controller
 		device pci 03.0 on  end # mini-hd audio
 
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# EC range is 0x800-0x9ff
 			register "gen1_dec" = "0x00fc0801"
 			register "gen2_dec" = "0x00fc0901"
@@ -83,6 +83,6 @@ chip soc/intel/broadwell
 			device pci 1f.2 on  end # SATA Controller
 			device pci 1f.3 off end # SMBus
 			device pci 1f.6 on  end # Thermal
-#		end
+		end
 	end
 end

src/mainboard/google/auron/variants/auron_paine/overridetree.cb

@@ -8,12 +8,12 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
 
 			device pci 1f.2 on  end # SATA Controller
-#		end
+		end
 	end
 end

src/mainboard/google/auron/variants/auron_yuna/overridetree.cb

@@ -8,12 +8,12 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x7"
 			register "sata_port1_gen3_dtle" = "0x5"
 
 			device pci 1f.2 on  end # SATA Controller
-#		end
+		end
 	end
 end

src/mainboard/google/auron/variants/buddy/overridetree.cb

@@ -10,7 +10,7 @@ chip soc/intel/broadwell
 	register "s0ix_enable" = "0"
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			register "sata_devslp_disable" = "0x1"
 
 			register "sio_i2c0_voltage" = "1" # 1.8V
@@ -36,6 +36,6 @@ chip soc/intel/broadwell
 			device pci 1c.3 on  end # PCIe Port #4 - WLAN (becomes RP2)
 			device pci 1f.2 on  end # SATA Controller
 			device pci 1f.3 on  end # SMBus
-#		end
+		end
 	end
 end

src/mainboard/google/auron/variants/gandof/overridetree.cb

@@ -8,12 +8,12 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
 
 			device pci 1f.2 on  end # SATA Controller
-#		end
+		end
 	end
 end

src/mainboard/google/auron/variants/lulu/overridetree.cb

@@ -8,12 +8,12 @@ chip soc/intel/broadwell
 	register "gpu_panel_power_backlight_off_delay" = "2100"	# 210ms
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# DTLE DATA / EDGE values
 			register "sata_port0_gen3_dtle" = "0x5"
 			register "sata_port1_gen3_dtle" = "0x5"
 
 			device pci 1f.2 on  end # SATA Controller
-#		end
+		end
 	end
 end

src/mainboard/google/auron/variants/samus/overridetree.cb

@@ -17,7 +17,7 @@ chip soc/intel/broadwell
 	register "s0ix_enable" = "0"
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			register "sata_port0_gen3_tx" = "0x72"
 
 			# Set I2C0 to 1.8V
@@ -37,6 +37,6 @@ chip soc/intel/broadwell
 			device pci 1c.2 on  end # PCIe Port #3
 			device pci 1d.0 off end # USB2 EHCI
 			device pci 1f.2 on  end # SATA Controller
-#		end
+		end
 	end
 end

src/mainboard/google/jecht/devicetree.cb

@@ -18,7 +18,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on end # vga controller
 		device pci 03.0 on end # mini-hd audio
 
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# SuperIO range is 0x700-0x73f
 			register "gen2_dec" = "0x003c0701"
 
@@ -113,6 +113,6 @@ chip soc/intel/broadwell
 			device pci 1f.2 on end # SATA Controller
 			device pci 1f.3 on end # SMBus
 			device pci 1f.6 on end # Thermal
-#		end
+		end
 	end
 end

src/mainboard/intel/wtm2/devicetree.cb

@@ -17,7 +17,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end	# vga controller
 		device pci 03.0 on  end	# mini-hd audio
 
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			register "alt_gp_smi_en" = "0x0000"
 			register "gpe0_en_1" = "0x00000400"
 			register "gpe0_en_2" = "0x00000000"
@@ -55,6 +55,6 @@ chip soc/intel/broadwell
 			device pci 1f.2 on  end	# SATA Controller
 			device pci 1f.3 on  end	# SMBus
 			device pci 1f.6 on  end	# Thermal
-#		end
+		end
 	end
 end

src/mainboard/purism/librem_bdw/devicetree.cb

@@ -24,7 +24,7 @@ chip soc/intel/broadwell
 		device pci 02.0 on  end # vga controller
 		device pci 03.0 on  end # mini-hd audio
 
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# EC host command ranges are in 0x380-0x383 & 0x80-0x8f
 			register "gen1_dec" = "0x00000381"
 			register "gen2_dec" = "0x000c0081"
@@ -57,6 +57,6 @@ chip soc/intel/broadwell
 			device pci 1f.2 on  end # SATA Controller
 			device pci 1f.3 on  end # SMBus
 			device pci 1f.6 off end # Thermal
-#		end
+		end
 	end
 end

src/mainboard/purism/librem_bdw/variants/librem13v1/overridetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/broadwell
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# Port 0 is HDD
 			# Port 3 is M.2 NGFF
 			register "sata_port_map" = "0x9"
@@ -11,6 +11,6 @@ chip soc/intel/broadwell
 			register "sata_port3_gen3_dtle" = "9"
 
 			device pci 1c.2 on  end # PCIe Port #3 - LAN
-#		end
+		end
 	end
 end

src/mainboard/purism/librem_bdw/variants/librem15v2/overridetree.cb

@@ -1,7 +1,7 @@
 chip soc/intel/broadwell
 
 	device domain 0 on
-#		chip soc/intel/broadwell/pch
+		chip soc/intel/broadwell/pch
 			# Port 0 is HDD
 			# Port 1 is M.2 NGFF
 			register "sata_port_map" = "0x3"
@@ -11,6 +11,6 @@ chip soc/intel/broadwell
 			register "sata_port1_gen3_dtle" = "9"
 
 			device pci 1d.0 on  end # USB2 EHCI
-#		end
+		end
 	end
 end

src/soc/intel/broadwell/adsp.c

@@ -14,11 +14,11 @@
 #include <soc/pch.h>
 #include <soc/ramstage.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
 
 static void adsp_init(struct device *dev)
 {
-	config_t *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 	struct resource *bar0, *bar1;
 	u32 tmp32;
 

src/soc/intel/broadwell/chip.h

@@ -7,70 +7,6 @@
 #include <stdint.h>
 
 struct soc_intel_broadwell_config {
-	/* GPE configuration */
-	uint32_t gpe0_en_1;
-	uint32_t gpe0_en_2;
-	uint32_t gpe0_en_3;
-	uint32_t gpe0_en_4;
-
-	/* GPIO SMI configuration */
-	uint32_t alt_gp_smi_en;
-
-	/* IDE configuration */
-	uint8_t sata_port_map;
-	uint32_t sata_port0_gen3_tx;
-	uint32_t sata_port1_gen3_tx;
-	uint32_t sata_port2_gen3_tx;
-	uint32_t sata_port3_gen3_tx;
-	uint32_t sata_port0_gen3_dtle;
-	uint32_t sata_port1_gen3_dtle;
-	uint32_t sata_port2_gen3_dtle;
-	uint32_t sata_port3_gen3_dtle;
-
-	/*
-	 * SATA DEVSLP Mux
-	 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
-	 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
-	 */
-	uint8_t sata_devslp_mux;
-
-	/*
-	 * DEVSLP Disable
-	 * 0: DEVSLP is enabled
-	 * 1: DEVSLP is disabled
-	 */
-	uint8_t sata_devslp_disable;
-
-	/* Generic IO decode ranges */
-	uint32_t gen1_dec;
-	uint32_t gen2_dec;
-	uint32_t gen3_dec;
-	uint32_t gen4_dec;
-
-	/* Enable linear PCIe Root Port function numbers starting at zero */
-	uint8_t pcie_port_coalesce;
-
-	/* Force root port ASPM configuration with port bitmap */
-	uint8_t pcie_port_force_aspm;
-
-	/* Put SerialIO devices into ACPI mode instead of a PCI device */
-	uint8_t sio_acpi_mode;
-
-	/* I2C voltage select: 0=3.3V 1=1.8V */
-	uint8_t sio_i2c0_voltage;
-	uint8_t sio_i2c1_voltage;
-
-	/* Enable ADSP power gating features */
-	uint8_t adsp_d3_pg_enable;
-	uint8_t adsp_sram_pg_enable;
-
-	/*
-	 * Clock Disable Map:
-	 * [21:16] = CLKOUT_PCIE# 5-0
-	 *    [24] = CLKOUT_ITPXDP
-	 */
-	uint32_t icc_clock_disable;
-
 	/*
 	 * Digital Port Hotplug Enable:
 	 *  0x04 = Enabled, 2ms short pulse
@@ -107,9 +43,6 @@ struct soc_intel_broadwell_config {
 
 	struct i915_gpu_controller_info gfx;
 
-	/* Enable S0iX support */
-	int s0ix_enable;
-
 	/*
 	 * Minimum voltage for C6/C7 state:
 	 * 0x67 = 1.6V (full swing)
@@ -132,9 +65,8 @@ struct soc_intel_broadwell_config {
 	/* Enable slow VR ramp rate */
 	int vr_slow_ramp_rate_enable;
 
-	/* Deep SX enable */
-	int deep_sx_enable_ac;
-	int deep_sx_enable_dc;
+	/* Enable S0iX support */
+	int s0ix_enable;
 
 	/* TCC activation offset */
 	uint32_t tcc_offset;

src/soc/intel/broadwell/include/soc/ramstage.h

@@ -8,7 +8,6 @@
 
 void broadwell_init_pre_device(void *chip_info);
 void broadwell_init_cpus(struct device *dev);
-void broadwell_pch_enable_dev(struct device *dev);
 
 #if CONFIG(HAVE_REFCODE_BLOB)
 void broadwell_run_reference_code(void);

src/soc/intel/broadwell/lpc.c

@@ -24,7 +24,7 @@
 #include <soc/pm.h>
 #include <soc/ramstage.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
 #include <acpi/acpigen.h>
 #include <southbridge/intel/common/rtc.h>
 
@@ -130,7 +130,7 @@ static void pch_power_options(struct device *dev)
 	u16 reg16;
 	const char *state;
 	/* Get the chip configuration */
-	config_t *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 	int pwr_on = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 
 	/* Which state do we want to goto after g3 (power restored)?
@@ -336,7 +336,7 @@ static void pch_enable_mphy(void)
 
 static void pch_init_deep_sx(struct device *dev)
 {
-	config_t *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 
 	if (config->deep_sx_enable_ac) {
 		RCBA32_OR(DEEP_S3_POL, DEEP_S3_EN_AC);
@@ -567,7 +567,7 @@ static void pch_lpc_add_gen_io_resources(struct device *dev, int reg_value,
 static void pch_lpc_add_io_resources(struct device *dev)
 {
 	struct resource *res;
-	config_t *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 
 	/* Add the default claimed IO range for the LPC device. */
 	res = new_resource(dev, 0);

src/soc/intel/broadwell/me.c

@@ -26,7 +26,7 @@
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
 
 #if CONFIG(CHROMEOS)
 #include <vendorcode/google/chromeos/chromeos.h>
@@ -950,7 +950,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, struct device *dev)
 /* Check whether ME is present and do basic init */
 static void intel_me_init(struct device *dev)
 {
-	config_t *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 	me_bios_path path = intel_me_path(dev);
 	me_bios_payload mbp_data;
 	int mbp_ret;

src/soc/intel/broadwell/pch.c

@@ -166,10 +166,16 @@ void pch_disable_devfn(struct device *dev)
 	}
 }
 
-void broadwell_pch_enable_dev(struct device *dev)
+static void broadwell_pch_enable_dev(struct device *dev)
 {
 	u16 reg16;
 
+	if (dev->path.type != DEVICE_PATH_PCI)
+		return;
+
+	if (dev->ops && dev->ops->enable)
+		return;
+
 	/* These devices need special enable/disable handling */
 	switch (PCI_SLOT(dev->path.pci.devfn)) {
 	case PCH_DEV_SLOT_PCIE:
@@ -195,4 +201,9 @@ void broadwell_pch_enable_dev(struct device *dev)
 	}
 }
 
+struct chip_operations soc_intel_broadwell_pch_ops = {
+	CHIP_NAME("Intel Broadwell PCH")
+	.enable_dev = &broadwell_pch_enable_dev,
+};
+
 #endif

src/soc/intel/broadwell/pch/chip.h

@@ -0,0 +1,78 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_INTEL_BROADWELL_PCH_CHIP_H_
+#define _SOC_INTEL_BROADWELL_PCH_CHIP_H_
+
+#include <stdint.h>
+
+struct soc_intel_broadwell_pch_config {
+	/* GPE configuration */
+	uint32_t gpe0_en_1;
+	uint32_t gpe0_en_2;
+	uint32_t gpe0_en_3;
+	uint32_t gpe0_en_4;
+
+	/* GPIO SMI configuration */
+	uint32_t alt_gp_smi_en;
+
+	/* IDE configuration */
+	uint8_t sata_port_map;
+	uint32_t sata_port0_gen3_tx;
+	uint32_t sata_port1_gen3_tx;
+	uint32_t sata_port2_gen3_tx;
+	uint32_t sata_port3_gen3_tx;
+	uint32_t sata_port0_gen3_dtle;
+	uint32_t sata_port1_gen3_dtle;
+	uint32_t sata_port2_gen3_dtle;
+	uint32_t sata_port3_gen3_dtle;
+
+	/*
+	 * SATA DEVSLP Mux
+	 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
+	 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
+	 */
+	uint8_t sata_devslp_mux;
+
+	/*
+	 * DEVSLP Disable
+	 * 0: DEVSLP is enabled
+	 * 1: DEVSLP is disabled
+	 */
+	uint8_t sata_devslp_disable;
+
+	/* Generic IO decode ranges */
+	uint32_t gen1_dec;
+	uint32_t gen2_dec;
+	uint32_t gen3_dec;
+	uint32_t gen4_dec;
+
+	/* Enable linear PCIe Root Port function numbers starting at zero */
+	uint8_t pcie_port_coalesce;
+
+	/* Force root port ASPM configuration with port bitmap */
+	uint8_t pcie_port_force_aspm;
+
+	/* Put SerialIO devices into ACPI mode instead of a PCI device */
+	uint8_t sio_acpi_mode;
+
+	/* I2C voltage select: 0=3.3V 1=1.8V */
+	uint8_t sio_i2c0_voltage;
+	uint8_t sio_i2c1_voltage;
+
+	/* Enable ADSP power gating features */
+	uint8_t adsp_d3_pg_enable;
+	uint8_t adsp_sram_pg_enable;
+
+	/*
+	 * Clock Disable Map:
+	 * [21:16] = CLKOUT_PCIE# 5-0
+	 *    [24] = CLKOUT_ITPXDP
+	 */
+	uint32_t icc_clock_disable;
+
+	/* Deep SX enable */
+	int deep_sx_enable_ac;
+	int deep_sx_enable_dc;
+};
+
+#endif

src/soc/intel/broadwell/pcie.c

@@ -13,7 +13,7 @@
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
 #include <soc/rcba.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
 #include <soc/cpu.h>
 #include <delay.h>
 
@@ -121,7 +121,7 @@ static void root_port_init_config(struct device *dev)
 		root_port_config_update_gbe_port();
 
 		pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4));
-		config_t *config = config_of(dev);
+		const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 		rpc.coalesce = config->pcie_port_coalesce;
 	}
 
@@ -436,7 +436,7 @@ static void pcie_add_0x0202000_iobp(u32 reg)
 
 static void pch_pcie_early(struct device *dev)
 {
-	config_t *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 	int do_aspm = 0;
 	int rp = root_port_number(dev);
 

src/soc/intel/broadwell/romstage/pch.c

@@ -12,7 +12,7 @@
 #include <soc/rcba.h>
 #include <soc/romstage.h>
 #include <soc/smbus.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
 
 static void pch_route_interrupts(void)
 {
@@ -52,9 +52,9 @@ static void pch_route_interrupts(void)
 static void pch_enable_lpc(void)
 {
 	/* Lookup device tree in romstage */
-	const config_t *config;
+	const struct device *const dev = pcidev_on_root(0x1f, 0);
 
-	config = config_of_soc();
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 
 	pci_write_config32(PCH_DEV_LPC, LPC_GEN1_DEC, config->gen1_dec);
 	pci_write_config32(PCH_DEV_LPC, LPC_GEN2_DEC, config->gen2_dec);

src/soc/intel/broadwell/sata.c

@@ -11,7 +11,7 @@
 #include <soc/ramstage.h>
 #include <soc/rcba.h>
 #include <soc/sata.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
 
 static inline u32 sir_read(struct device *dev, int idx)
 {
@@ -27,7 +27,7 @@ static inline void sir_write(struct device *dev, int idx, u32 value)
 
 static void sata_init(struct device *dev)
 {
-	config_t *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 	u32 reg32;
 	u8 *abar;
 	u16 reg16;
@@ -256,7 +256,7 @@ static void sata_init(struct device *dev)
 static void sata_enable(struct device *dev)
 {
 	/* Get the chip configuration */
-	config_t *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 	u16 map = 0x0060;
 
 	map |= (config->sata_port_map ^ 0xf) << 8;

src/soc/intel/broadwell/serialio.c

@@ -14,7 +14,7 @@
 #include <soc/ramstage.h>
 #include <soc/rcba.h>
 #include <soc/serialio.h>
-#include <soc/intel/broadwell/chip.h>
+#include <soc/intel/broadwell/pch/chip.h>
 
 /* Set D3Hot Power State in ACPI mode */
 static void serialio_enable_d3hot(struct resource *res)
@@ -156,7 +156,7 @@ static void serialio_init_once(int acpi_mode)
 
 static void serialio_init(struct device *dev)
 {
-	config_t *config = config_of(dev);
+	const struct soc_intel_broadwell_pch_config *config = config_of(dev);
 	struct resource *bar0, *bar1;
 	int sio_index = -1;
 

src/soc/intel/broadwell/systemagent.c

@@ -472,12 +472,6 @@ static void broadwell_enable(struct device *dev)
 		dev->ops = &pci_domain_ops;
 	} else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
 		dev->ops = &cpu_bus_ops;
-	} else if (dev->path.type == DEVICE_PATH_PCI) {
-		/* Handle PCH device enable */
-		if (PCI_SLOT(dev->path.pci.devfn) > SA_DEV_SLOT_MINIHD &&
-		    (dev->ops == NULL || dev->ops->enable == NULL)) {
-			broadwell_pch_enable_dev(dev);
-		}
 	}
 }