baytrail: print dram configuration

After running the MRC blob print out some information
on the training: MRC version, number channels, DDR3
type, and DRAM frequency.

Example output:
MRC v0.90
2 channels of DDR3 @ 1066MHz

Apparently there are two dunit IOSF ports -- 1 for each
channel. However, certain registers really on live in
channel 0. Thus, there was some changes to dunit support
in the iosf area.

BUG=chrome-os-partner:22875
BRANCH=None
TEST=Built and booted bayleybay in different configs.

Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172770
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4882
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

src/soc/intel/baytrail/baytrail/iosf.h

@@ -58,16 +58,21 @@ uint32_t iosf_bunit_read(int reg);
 void iosf_bunit_write(int reg, uint32_t val);
 uint32_t iosf_dunit_read(int reg);
 void iosf_dunit_write(int reg, uint32_t val);
+/* Some registers are per channel while the gloals live in dunit 0 */
+uint32_t iosf_dunit_ch0_read(int reg);
+uint32_t iosf_dunit_ch1_read(int reg);
 uint32_t iosf_punit_read(int reg);
 void iosf_punit_write(int reg, uint32_t val);
 
 /* IOSF ports. */
 #define IOSF_PORT_AUNIT		0x00 /* IO Arbiter unit */
 #define IOSF_PORT_SYSMEMC	0x01 /* System Memory Controller */
+#define IOSF_PORT_DUNIT_CH0	0x07 /* DUNIT Channel 0 */
 #define IOSF_PORT_CPU_BUS	0x02 /* CPU Bus Interface Controller */
 #define IOSF_PORT_BUNIT		0x03 /* System Memroy Arbiter/Bunit */
 #define IOSF_PORT_PMC		0x04 /* Power Management Controller */
 #define IOSF_PORT_GFX		0x06 /* Graphics Adapter */
+#define IOSF_PORT_DUNIT_CH1	0x07 /* DUNIT Channel 1 */
 #define IOSF_PORT_SYSMEMIO	0x0c /* System Memory IO */
 #define IOSF_PORT_USBPHY	0x43 /* USB PHY */
 #define IOSF_PORT_SATAPHY	0xa3 /* SATA PHY */
@@ -120,10 +125,12 @@ void iosf_punit_write(int reg, uint32_t val);
  */
 
 #define DRP			0x00
-# define DRP_CH0_RANK0_EN	(0x01 << 0)
+# define DRP_DIMM0_RANK0_EN	(0x01 << 0)
-# define DRP_CH0_RANK1_EN	(0x01 << 1)
+# define DRP_DIMM0_RANK1_EN	(0x01 << 1)
-# define DRP_CH1_RANK0_EN	(0x01 << 2)
+# define DRP_DIMM1_RANK0_EN	(0x01 << 2)
-# define DRP_CH1_RANK1_EN	(0x01 << 3)
+# define DRP_DIMM1_RANK1_EN	(0x01 << 3)
+# define DRP_RANK_MASK (DRP_DIMM0_RANK0_EN | DRP_DIMM0_RANK1_EN | \
+			DRP_DIMM1_RANK0_EN | DRP_DIMM1_RANK1_EN)
 #define DTR0			0x01
 # define DTR0_SPEED_MASK	0x03
 # define DTR0_SPEED_800		0x00

src/soc/intel/baytrail/iosf.c

@@ -70,6 +70,21 @@ uint32_t iosf_dunit_read(int reg)
 	return read_iosf_reg(MDR_REG);
 }
 
+uint32_t iosf_dunit_ch0_read(int reg)
+{
+	return iosf_dunit_read(reg);
+}
+
+uint32_t iosf_dunit_ch1_read(int reg)
+{
+	uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SYSMEMC) |
+	              IOSF_PORT(IOSF_PORT_DUNIT_CH1) | IOSF_REG(reg) |
+	              IOSF_BYTE_EN;
+
+	write_iosf_reg(MCR_REG, cr);
+	return read_iosf_reg(MDR_REG);
+}
+
 void iosf_dunit_write(int reg, uint32_t val)
 {
 	uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SYSMEMC) |

src/soc/intel/baytrail/romstage/raminit.c

@@ -26,6 +26,7 @@
 #include <baytrail/gpio.h>
 #include <baytrail/mrc_cache.h>
 #include <baytrail/iomap.h>
+#include <baytrail/iosf.h>
 #include <baytrail/pci_devs.h>
 #include <baytrail/romstage.h>
 
@@ -57,6 +58,48 @@ static void ABI_X86 send_to_console(unsigned char b)
 	console_tx_byte(b);
 }
 
+static void print_dram_info(void)
+{
+	const int mrc_ver_reg = 0xf0;
+	const uint32_t soc_dev = PCI_DEV(0, SOC_DEV, SOC_FUNC);
+	uint32_t reg;
+	int num_channels;
+	int speed;
+	uint32_t ch0;
+	uint32_t ch1;
+
+	reg = pci_read_config32(soc_dev, mrc_ver_reg);
+
+	printk(BIOS_INFO, "MRC v%d.%02d\n", (reg >> 8) & 0xff, reg & 0xff);
+
+	/* Number of channels enabled and DDR3 type. Determine number of
+	 * channels by keying of the rank enable bits [3:0]. * */
+	ch0 = iosf_dunit_ch0_read(DRP);
+	ch1 = iosf_dunit_ch1_read(DRP);
+	num_channels = 0;
+	if (ch0 & DRP_RANK_MASK)
+		num_channels++;
+	if (ch1 & DRP_RANK_MASK)
+		num_channels++;
+
+	printk(BIOS_INFO, "%d channels of %sDDR3 @ ", num_channels,
+	       (reg & (1 << 22)) ? "LP" : "");
+
+	/* DRAM frequency -- all channels run at same frequency. */
+	reg = iosf_dunit_read(DTR0);
+	switch (reg & 0x3) {
+	case 0:
+		speed = 800; break;
+	case 1:
+		speed = 1066; break;
+	case 2:
+		speed = 1333; break;
+	case 3:
+		speed = 1600; break;
+	}
+	printk(BIOS_INFO, "%dMHz\n", speed);
+}
+
 void raminit(struct mrc_params *mp, int prev_sleep_state)
 {
 	int ret;
@@ -87,6 +130,8 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
 
 	ret = mrc_entry(mp);
 
+	print_dram_info();
+
 	cbmem_initialize_empty();
 
 	printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret);