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sb/intel/bd82x6x: Remove setting up lpc decode ranges in ramstage 

This is now done during the romstage.

Change-Id: I7c1a848ae871ffb73c09ee88f96331d6b823e39d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Arthur Heymans 2019-08-18 10:02:10 +02:00 committed by Patrick Georgi
parent a31e6e8497
commit 3cde494000
1 changed files with 1 additions and 19 deletions
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20
src/southbridge/intel/bd82x6x/lpc.c
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@ -460,18 +460,6 @@ static void pch_fixups(struct device *dev)
RCBA32_OR(LCTL, 0x3);
}
static void pch_decode_init(struct device *dev)
{
config_t *config = dev->chip_info;
printk(BIOS_DEBUG, "pch_decode_init\n");
pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec);
pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec);
pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec);
pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
}
static void pch_spi_init(const struct device *const dev)
{
const config_t *const config = dev->chip_info;
@ -681,12 +669,6 @@ static void pch_lpc_read_resources(struct device *dev)
}
}
static void pch_lpc_enable_resources(struct device *dev)
{
pch_decode_init(dev);
return pci_dev_enable_resources(dev);
}
static void pch_lpc_enable(struct device *dev)
{
/* Enable PCH Display Port */
@ -910,7 +892,7 @@ static struct pci_operations pci_ops = {
static struct device_operations device_ops = {
.read_resources = pch_lpc_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pch_lpc_enable_resources,
.enable_resources = pci_dev_enable_resources,
.write_acpi_tables = acpi_write_hpet,
.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
.acpi_fill_ssdt_generator = southbridge_fill_ssdt,