mb/google/brox: Align GPIO reset with HW spreadsheet
Did a pass through HW team's brox speadsheet and aligned the gpio.c file with it. The changes in this CL are to fix the pad's reset field as needed. See "Intel SoCs" section in https://doc.coreboot.org/getting_started/gpio.html for reset definitions. BUG=b:300690448,b:316180020 BRANCH=NONE TEST=emerge-brox coreboot Change-Id: I4285136184c648adb9dc97748bd6b01cba3f8ddd Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Shelley Chen
Nick Vaccaro
parent
afa76c5ca0
commit
3ced071396
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@ -68,11 +68,11 @@ static const struct pad_config gpio_table[] = {
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/* GPP_A15 : [NF1: USB_OC2# NF2: DDSP_HPD4 NF4: DISP_MISC4 NF6: USB_C_GPP_A15] ==> USB_A1_OC_ODL */
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PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
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/* GPP_A16 : [NF1: USB_OC3# NF4: ISH_GP5 NF6: USB_C_GPP_A16] ==> TABLET_MODE_ODL */
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PAD_CFG_GPI(GPP_A16, NONE, DEEP),
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PAD_CFG_GPI(GPP_A16, NONE, PLTRST),
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/* GPP_A17 : [NF4: DISP_MISCC NF6: USB_C_GPP_A17] ==> SOC_GPP_A17 */
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PAD_NC(GPP_A17, NONE),
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/* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> HDMI_HPD */
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PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_A18, NONE, PLTRST, NF1),
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/* GPP_A19 : [NF1: DDSP_HPD1 NF4: DISP_MISC1 NF6: USB_C_GPP_A19] ==> USB_C2_AUX_DC_P */
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PAD_CFG_NF(GPP_A19, NONE, DEEP, NF6),
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/* GPP_A20 : [NF1: DDSP_HPD2 NF4: DISP_MISC2 NF6: USB_C_GPP_A20] ==> USB_C2_AUX_DC_N */
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@ -80,7 +80,7 @@ static const struct pad_config gpio_table[] = {
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/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> SOC_GPP_A21 (NC) */
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PAD_NC(GPP_A21, NONE),
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/* GPP_A22 : DDPC_CTRLDATA ==> PD_SOC_DBG_L */
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PAD_CFG_GPI(GPP_A22, NONE, DEEP),
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PAD_CFG_GPI(GPP_A22, NONE, PLTRST),
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/* GPP_A23 : ESPI_CS1_L ==> RAM_INTERLEAVED (NC) */
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PAD_NC(GPP_A23, NONE),
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@ -95,9 +95,9 @@ static const struct pad_config gpio_table[] = {
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/* GPP_B4 : PROC_GP3/ISH_GP5B ==> BOARD_ID9 (NC) */
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PAD_NC(GPP_B4, NONE),
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/* GPP_B5 : [NF1: ISH_I2C0_SDA NF2: I2C2_SDA NF6: USB_C_GPP_B5] ==> ISH_I2C_SENSOR_SDA */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_B5, NONE, PLTRST, NF2),
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/* GPP_B6 : [NF1: ISH_I2C0_SCL NF2: I2C2_SCL NF6: USB_C_GPP_B6] ==> ISH_I2C_SENSOR_SCL */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_B6, NONE, PLTRST, NF2),
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/* GPP_B7 : [NF1: ISH_I2C1_SDA NF2: I2C3_SDA NF6: USB_C_GPP_B7] ==> SOC_I2C3_SDA (NC) */
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PAD_NC(GPP_B7, NONE),
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/* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> SOC_I2C3_SCL (NC) */
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@ -111,7 +111,7 @@ static const struct pad_config gpio_table[] = {
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/* GPP_B14 : [NF1: SPKR NF2: TIME_SYNC1 NF4: SATA_LED# NF5: ISH_GP6 NF6: USB_C_GPP_B14] ==> ACZ_SPKR (NC) */
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PAD_NC(GPP_B14, NONE),
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/* GPP_B15 : [NF2: TIME_SYNC0 NF5: ISH_GP7 NF6: USB_C_GPP_B15] ==> LID_OPEN_Q */
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PAD_CFG_GPI(GPP_B15, NONE, DEEP),
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PAD_CFG_GPI(GPP_B15, NONE, PLTRST),
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/* b/316421831: GPP_B16/17 need to be enabled when ISH is enabled later on */
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/* GPP_B16 : [NF2: I2C5_SDA NF4: ISH_I2C2_SDA NF6: USB_C_GPP_B16] ==> ISH_I2C_EC_SDA (NC) */
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PAD_NC(GPP_B16, NONE),
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@ -120,7 +120,7 @@ static const struct pad_config gpio_table[] = {
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/* GPP_B18 : GPP_B18 ==> GPP_B18_STRAP */
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PAD_NC(GPP_B18, NONE),
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/* GPP_B23 : SML1ALERT_L/PCHHOT_L ==> PCHHOT_ODL_STRAP */
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PAD_CFG_GPI(GPP_B23, NONE, DEEP),
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PAD_CFG_GPI(GPP_B23, NONE, PLTRST),
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/* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SOC_GPP_C0 (NC) */
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PAD_NC(GPP_C0, NONE),
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@ -139,9 +139,9 @@ static const struct pad_config gpio_table[] = {
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/* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA (NC) */
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PAD_NC(GPP_C7, NONE),
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/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> SENSOR_MODE1_PCH_EC_PCH_WAKE_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_D0, NONE, PLTRST, EDGE_SINGLE, INVERT),
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/* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> SENSOR_MODE2_PCH_EC_PCH_INT_ODL */
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/* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_WAKE_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_D0, NONE, DEEP, EDGE_SINGLE, INVERT),
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/* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_INT_ODL */
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PAD_CFG_GPI_INT(GPP_D1, NONE, PLTRST, LEVEL),
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/* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */
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PAD_NC(GPP_D2, NONE),
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@ -168,7 +168,7 @@ static const struct pad_config gpio_table[] = {
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/* GPP_D13 : [NF1: ISH_UART0_RXD NF3: I2C6_SDA NF6: USB_C_GPP_D13] ==> UART0_ISH_RX_DBG_TX */
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PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
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/* GPP_D14 : [NF1: ISH_UART0_TXD NF3: I2C6_SCL NF6: USB_C_GPP_D14] ==> UART0_ISH_TX_DBG_RX */
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PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_D14, NONE, PLTRST, NF1),
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/* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> SOC_ISH_UART0_RTS_L (NC) */
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PAD_NC(GPP_D15, NONE),
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/* GPP_D16 : ISH_UART0_CTS_L/I2C7B_SCL ==> SOC_GPP_D16 (NC) */
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@ -189,7 +189,7 @@ static const struct pad_config gpio_table[] = {
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/* GPP_E3 : [NF1: PROC_GP0 NF6: USB_C_GPP_E3] ==> TCHPAD_INT_ODL */
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PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, INVERT),
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/* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> USB4_BB_RT_FORCE_PWR */
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PAD_CFG_GPO(GPP_E4, 1, DEEP),
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PAD_CFG_GPO(GPP_E4, 1, PLTRST),
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/* GPP_E5 : [NF1: DEVSLP1 NF6: USB_C_GPP_E5 NF7: SRCCLK_OE6#] ==> SOC_GPP_E5 (NC) */
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PAD_NC(GPP_E5, NONE),
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/* GPP_E6 : [NF2: THC0_SPI1_RST# NF6: USB_C_GPP_E6] ==> SOC_GPP_E6_STRAP (NC) */
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@ -201,17 +201,17 @@ static const struct pad_config gpio_table[] = {
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/* GPP_E9 : [NF1: USB_OC0# NF2: ISH_GP4 NF6: USB_C_GPP_E9] ==> SOC_GPP_E9 (NC) */
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PAD_NC(GPP_E9, NONE),
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/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_E10, NONE, DEEP),
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PAD_CFG_GPI(GPP_E10, NONE, PLTRST),
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/* GPP_E11 : [NF2: THC0_SPI1_CLK NF6: USB_C_GPP_E11 NF7: GSPI0_CLK] ==> SOC_GPP_E11 (NC) */
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PAD_NC(GPP_E11, NONE),
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/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_E12, NONE, DEEP),
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PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
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/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_E13, NONE, DEEP),
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PAD_CFG_GPI(GPP_E13, NONE, PLTRST),
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/* GPP_E14 : [NF1: DDSP_HPDA NF2: DISP_MISC_A NF6: USB_C_GPP_E14] ==> SOC_EDP_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E14, NONE, PLTRST, NF1),
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/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_E15, NONE, DEEP),
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PAD_CFG_GPI(GPP_E15, NONE, PLTRST),
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/* GPP_E16 : SRCCLKREQ8_L ==> BOARD_ID6 (NC) */
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PAD_NC(GPP_E16, NONE),
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/* GPP_E17 : [NF2: THC0_SPI1_INT# NF6: USB_C_GPP_E17] ==> SOC_GPP_E17 (NC) */
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@ -244,9 +244,9 @@ static const struct pad_config gpio_table[] = {
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/* GPP_F6 : [NF1: CNV_PA_BLANKING NF6: USB_C_GPP_F6] ==> SOC_GPP_F6 (NC)*/
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PAD_NC(GPP_F6, NONE),
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/* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */
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PAD_CFG_GPO(GPP_F7, 0, DEEP),
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PAD_CFG_GPO(GPP_F7, 0, PLTRST),
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/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
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PAD_CFG_GPO(GPP_F9, 1, PLTRST),
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PAD_CFG_GPO(GPP_F9, 1, DEEP),
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/* GPP_F10 : GPP_F10 ==> GPP_F10_STRAP (NC) */
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PAD_NC(GPP_F10, NONE),
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/* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> SOC_GPP_F11 (NC) */
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@ -260,11 +260,11 @@ static const struct pad_config gpio_table[] = {
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/* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 NF6: USB_C_GPP_F15] ==> SOC_GPP_F15 */
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PAD_NC(GPP_F15, NONE),
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/* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# NF6: USB_C_GPP_F16] ==> PCH_TCHSCR_REPORT_EN */
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PAD_CFG_GPO(GPP_F16, 0, DEEP),
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PAD_CFG_GPO(GPP_F16, 0, PLTRST),
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/* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */
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PAD_CFG_NF(GPP_F17, NONE, DEEP, NF3),
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/* GPP_F18 : [NF3: THC1_SPI2_INT# NF6: USB_C_GPP_F18] ==> TCHSCR_INT_ODL */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3),
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PAD_CFG_NF(GPP_F18, NONE, PLTRST, NF3),
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/* GPP_F19 : SRCCLKREQ6 ==> NC */
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PAD_NC(GPP_F19, NONE),
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/* GPP_F20 : [NF1: Reserved NF6: USB_C_GPP_F20] ==> SOC_GPP_F20 (NC) */
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@ -285,29 +285,29 @@ static const struct pad_config gpio_table[] = {
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/* GPP_H3 : [NF1: SX_EXIT_HOLDOFF# NF6: USB_C_GPP_H3] ==> WLAN_PCIE_WAKE_ODL (NC) */
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PAD_NC(GPP_H3, NONE),
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/* GPP_H4 : I2C0_SDA ==> PCH_I2C_TCHPAD_SDA */
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H4, NONE, PLTRST, NF1),
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/* GPP_H5 : [NF1: I2C0_SCL NF6: USB_C_GPP_H5] ==> PCH_I2C_TCHPAD_SCL */
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H5, NONE, PLTRST, NF1),
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/* GPP_H6 : [NF1: I2C1_SDA NF6: USB_C_GPP_H6] ==> PCH_I2C_TCHSCR_SDA */
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H6, NONE, PLTRST, NF1),
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/* GPP_H7 : [NF1: I2C1_SCL NF6: USB_C_GPP_H7] ==> PCH_I2C_TCHSCR_SCL */
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H7, NONE, PLTRST, NF1),
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/* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */
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PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
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/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
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/* GPP_H10 : [NF2: UART0_RXD NF3: M2_SKT2_CFG0 NF6: USB_C_GPP_H10] ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2),
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/* GPP_H11 : [NF2: UART0_TXD NF3: M2_SKT2_CFG1 NF6: USB_C_GPP_H11] ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2),
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/* GPP_H12 : [NF1: I2C7_SDA NF2: UART0_RTS# NF3: M2_SKT2_CFG2 NF4: ISH_GP6B NF5: DEVSLP0B NF6: USB_C_GPP_H12] ==> SOC_UART0_RTS_L (NC) */
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PAD_NC(GPP_H12, NONE),
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/* GPP_H13 : I2C7_SCL/UART0_CTS_L/M2_SKT2CFG3/ISH_GP7B/DEVSLK1B ==> BOARD_ID0 (NC) */
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PAD_NC(GPP_H13, NONE),
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/* GPP_H15 : [NF1: DDPB_CTRLCLK NF3: PCIE_LINK_DOWN NF6: USB_C_GPP_H15] ==> DDIB_HDMI_CTRLCLK */
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PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H15, NONE, PLTRST, NF1),
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/* GPP_H17 : [NF1: DDPB_CTRLDATA NF6: USB_C_GPP_H17] ==> DDIB_HDMI_CTRLDATA */
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PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_H17, NONE, PLTRST, NF1),
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/* GPP_H18 : [NF1: PROC_C10_GATE# NF6: USB_C_GPP_H18] ==> CPU_C10_GATE_L */
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
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/* GPP_H19 : SRCCLKREQ4_L ==> NC */
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@ -322,13 +322,13 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_H23, NONE),
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/* GPP_R0 : [NF1: HDA_BCLK NF2: I2S0_SCLK NF3: DMIC_CLK_B0 NF4: HDAPROC_BCLK] ==> HDA_HP_BCLK_R */
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PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_R0, NONE, PLTRST, NF1),
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/* GPP_R1 : [NF1: HDA_SYNC NF3: DMIC_CLK_B1] ==> HDA_HP_SYNC_R */
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PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_R1, NONE, PLTRST, NF1),
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/* GPP_R2 : [NF1: HDA_SDO NF2: I2S0_TXD NF4: HDAPROC_SDO] ==> HDA_HP_SDO_R */
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PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_R2, NONE, PLTRST, NF1),
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/* GPP_R3 : [NF1: HDA_SDI0 NF2: I2S0_RXD NF4: HDAPROC_SDI] ==> HDA_HP_SDI0 */
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PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_R3, NONE, PLTRST, NF1),
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/* GPP_R4 : HDA_RST_L/I2S2_SCLK/DMIC_CLK_A0 ==> SOC_GPP_R4 */
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PAD_NC(GPP_R4, NONE),
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/* GPP_R5 : HDA_SDI1/I2S2_SFRM/DMIC_DATA0 ==> SOC_GPP_R4 (NC) */
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@ -390,22 +390,22 @@ static const struct pad_config early_gpio_table[] = {
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/* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */
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PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
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/* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
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PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2),
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/* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
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PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
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PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2),
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/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */
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PAD_CFG_GPI(GPP_S0, NONE, DEEP),
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};
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static const struct pad_config romstage_gpio_table[] = {
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/* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_E10, NONE, DEEP),
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PAD_CFG_GPI(GPP_E10, NONE, PLTRST),
|
||||
/* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */
|
||||
PAD_CFG_GPI(GPP_E12, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E12, NONE, PLTRST),
|
||||
/* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */
|
||||
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E13, NONE, PLTRST),
|
||||
/* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */
|
||||
PAD_CFG_GPI(GPP_E15, NONE, DEEP),
|
||||
PAD_CFG_GPI(GPP_E15, NONE, PLTRST),
|
||||
/* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */
|
||||
PAD_CFG_GPO(GPP_F9, 1, DEEP),
|
||||
/* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */
|
||||
|
|
|
|||
Loading…
Reference in New Issue