Add support for dumping ACPI registers for i7
Signed-off-by: Warren Turkal <wt@penguintechs.org> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -21,6 +21,66 @@
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#include <stdio.h>
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#include <stdio.h>
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#include "inteltool.h"
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#include "inteltool.h"
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static const io_register_t ich10_pm_registers[] = {
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{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
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{ 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
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{ 0x04, 4, "PM1_CNT" }, // PM1 Control; ACPI pointer: PM1a_CNT_BLK
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{ 0x08, 4, "PM1_TMR" }, // PM1 Timer; ACPI pointer: PMTMR_BLK
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{ 0x0c, 4, "RESERVED" },
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{ 0x10, 4, "PROC_CNT" }, // Processor Control; ACPI pointer: P_BLK
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#if DANGEROUS_REGISTERS
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/* These registers return 0 on read, but reading them may cause
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* the system to enter Cx states, which might hang the system.
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*/
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{ 0x14, 1, "LV2 (Mobile)" },
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{ 0x15, 1, "LV3 (Mobile)" },
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{ 0x16, 1, "LV4 (Mobile)" },
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#endif
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{ 0x17, 2, "RESERVED" },
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{ 0x19, 1, "RESERVED" },
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{ 0x1a, 2, "RESERVED" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 8, "GPE0_STS" }, // General Purpose Event 0 Status; ACPI pointer: GPE0_BLK
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{ 0x2C, 4, "GPE0_EN" }, // General Purpose Event 0 Enables; ACPI pointer: GPE0_BLK+8
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{ 0x30, 4, "SMI_EN" },
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{ 0x34, 4, "SMI_STS" },
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{ 0x38, 2, "ALT_GP_SMI_EN" },
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{ 0x3a, 2, "ALT_GP_SMI_STS" },
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{ 0x3c, 1, "UPRWC" }, // USB Per-Port registers write control;
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{ 0x3d, 2, "RESERVED" },
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{ 0x3f, 1, "RESERVED" },
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{ 0x40, 2, "RESERVED" },
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{ 0x42, 1, "GPE_CNTL" },
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{ 0x43, 1, "RESERVED" },
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{ 0x44, 2, "DEVACT_STS" }, // Device Activity Status
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{ 0x46, 2, "RESERVED" },
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{ 0x48, 4, "RESERVED" },
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{ 0x4c, 4, "RESERVED" },
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{ 0x50, 1, "PM2_CNT (Mobile)" }, // PM2 Control (Mobile only); ACPI pointer: PM2a_CNT_BLK
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{ 0x51, 1, "RESERVED" },
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{ 0x52, 2, "RESERVED" },
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{ 0x54, 4, "C3_RES (Mobile)" },
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{ 0x58, 4, "RESERVED" },
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{ 0x5c, 4, "RESERVED" },
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/* Here start the TCO registers */
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{ 0x60, 2, "TCO_RLD" },
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{ 0x62, 1, "TCO_DAT_IN" },
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{ 0x63, 1, "TCO_DAT_OUT" },
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{ 0x64, 2, "TCO1_STS" },
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{ 0x66, 2, "TCO2_STS" },
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{ 0x68, 2, "TCO1_CNT" },
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{ 0x6a, 2, "TCO2_CNT" },
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{ 0x6c, 2, "TCO_MESSAGE" },
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{ 0x6e, 1, "TCO_WDCNT" },
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{ 0x6f, 1, "RESERVED" },
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{ 0x70, 1, "SW_IRQ_GEN" },
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{ 0x71, 1, "RESERVED" },
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{ 0x72, 2, "TCO_TMR" },
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{ 0x74, 4, "RESERVED" },
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{ 0x78, 4, "RESERVED" },
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{ 0x7c, 4, "RESERVED" },
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};
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static const io_register_t ich9_pm_registers[] = {
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static const io_register_t ich9_pm_registers[] = {
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{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
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{ 0x00, 2, "PM1_STS" }, // PM1 Status; ACPI pointer: PM1a_EVT_BLK
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{ 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
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{ 0x02, 2, "PM1_EN" }, // PM1 Enables; ACPI pointer: PM1a_EVT_BLK+2
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@ -473,6 +533,11 @@ int print_pmbase(struct pci_dev *sb)
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printf("\n============= PMBASE ============\n\n");
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printf("\n============= PMBASE ============\n\n");
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switch (sb->device_id) {
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_ICH10R:
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pmbase = pci_read_word(sb, 0x40) & 0xff80;
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pm_registers = ich10_pm_registers;
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size = ARRAY_SIZE(ich10_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH7:
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case PCI_DEVICE_ID_INTEL_ICH7:
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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