soc/intel/elkhartlake: Update PCI device definition
This change updates PCI device definition according to EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ibf7ef3c30deab5398361bc18fc63ac39fc914d8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48444 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Tan, Lean Sheng
Werner Zeh
parent
92fa1d9663
commit
3cf8a03730
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@ -17,7 +17,7 @@
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#include <soc/soc_chip.h>
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static const struct pcie_rp_group pch_rp_groups[] = {
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{ .slot = PCH_DEV_SLOT_PCIE, .count = 8 },
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{ .slot = PCH_DEV_SLOT_PCIE, .count = 7 },
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{ 0 }
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};
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@ -64,16 +64,17 @@ const char *soc_acpi_name(const struct device *dev)
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switch (dev->path.pci.devfn) {
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case SA_DEVFN_ROOT: return "MCHC";
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case SA_DEVFN_IPU: return "IPU0";
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case PCH_DEVFN_ISH: return "ISHB";
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case PCH_DEVFN_I2C6: return "I2C6";
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case PCH_DEVFN_I2C7: return "I2C7";
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case PCH_DEVFN_XHCI: return "XHCI";
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case PCH_DEVFN_I2C0: return "I2C0";
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case PCH_DEVFN_I2C1: return "I2C1";
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case PCH_DEVFN_I2C2: return "I2C2";
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case PCH_DEVFN_I2C3: return "I2C3";
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case PCH_DEVFN_SATA: return "SATA";
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case PCH_DEVFN_UART2: return "UAR2";
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case PCH_DEVFN_I2C4: return "I2C4";
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case PCH_DEVFN_I2C5: return "I2C5";
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case PCH_DEVFN_SATA: return "SATA";
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case PCH_DEVFN_PCIE1: return "RP01";
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case PCH_DEVFN_PCIE2: return "RP02";
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case PCH_DEVFN_PCIE3: return "RP03";
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@ -81,23 +82,16 @@ const char *soc_acpi_name(const struct device *dev)
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case PCH_DEVFN_PCIE5: return "RP05";
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case PCH_DEVFN_PCIE6: return "RP06";
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case PCH_DEVFN_PCIE7: return "RP07";
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case PCH_DEVFN_PCIE8: return "RP08";
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case PCH_DEVFN_PCIE9: return "RP09";
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case PCH_DEVFN_PCIE10: return "RP10";
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case PCH_DEVFN_PCIE11: return "RP11";
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case PCH_DEVFN_PCIE12: return "RP12";
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case PCH_DEVFN_UART0: return "UAR0";
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case PCH_DEVFN_UART1: return "UAR1";
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case PCH_DEVFN_UART2: return "UAR2";
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case PCH_DEVFN_GSPI0: return "SPI0";
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case PCH_DEVFN_GSPI1: return "SPI1";
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case PCH_DEVFN_GBE: return "GLAN";
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case PCH_DEVFN_GSPI2: return "SPI2";
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case PCH_DEVFN_GSPI3: return "SPI3";
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case PCH_DEVFN_EMMC: return "EMMC";
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case PCH_DEVFN_SDCARD: return "SDXC";
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case PCH_DEVFN_HDA: return "HDAS";
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case PCH_DEVFN_SMBUS: return "SBUS";
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case PCH_DEVFN_GBE: return "GLAN";
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}
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return NULL;
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@ -30,76 +30,58 @@
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#define SA_DEVFN_DPTF PCI_DEVFN(SA_DEV_SLOT_DPTF, 0)
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#define SA_DEV_DPTF PCI_DEV(0, SA_DEV_SLOT_DPTF, 0)
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#define SA_DEV_SLOT_TBT 0x07
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#define SA_DEVFN_TBT0 PCI_DEVFN(SA_DEV_SLOT_TBT, 0)
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#define SA_DEVFN_TBT1 PCI_DEVFN(SA_DEV_SLOT_TBT, 1)
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#define SA_DEVFN_TBT2 PCI_DEVFN(SA_DEV_SLOT_TBT, 2)
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#define SA_DEVFN_TBT3 PCI_DEVFN(SA_DEV_SLOT_TBT, 3)
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#define SA_DEV_TBT0 PCI_DEV(0, SA_DEV_SLOT_TBT, 0)
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#define SA_DEV_TBT1 PCI_DEV(0, SA_DEV_SLOT_TBT, 1)
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#define SA_DEV_TBT2 PCI_DEV(0, SA_DEV_SLOT_TBT, 2)
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#define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3)
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#define SA_DEV_SLOT_GNA 0x08
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#define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0)
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#define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0)
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#define SA_DEV_SLOT_IPU 0x05
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#define SA_DEVFN_IPU PCI_DEVFN(SA_DEV_SLOT_IPU, 0)
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#define SA_DEV_IPU PCI_DEV(0, SA_DEV_SLOT_IPU, 0)
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#define SA_DEV_SLOT_TRACEHUB 0x09
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#define SA_DEVFN_TRACEHUB PCI_DEVFN(SA_DEV_SLOT_TRACEHUB, 0)
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#define SA_DEV_TRACEHUB PCI_DEV(0, SA_DEV_SLOT_TRACEHUB, 0)
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/* PCH Devices */
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#define PCH_DEV_SLOT_SIO0 0x10
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#define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2)
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#define PCH_DEVFN_THC0 _PCH_DEVFN(SIO0, 6)
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#define PCH_DEVFN_THC1 _PCH_DEVFN(SIO0, 7)
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#define PCH_DEV_CNVI_BT _PCH_DEV(SIO0, 2)
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#define PCH_DEV_THC0 _PCH_DEV(SIO0, 6)
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#define PCH_DEV_THC1 _PCH_DEV(SIO0, 7)
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#define PCH_DEV_SLOT_IEH 0x10
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#define PCH_DEVFN_I2C6 _PCH_DEVFN(IEH, 0)
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#define PCH_DEVFN_I2C7 _PCH_DEVFN(IEH, 1)
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#define PCH_DEVFN_IEH _PCH_DEVFN(IEH, 5)
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#define PCH_DEV_I2C6 _PCH_DEV(IEH, 0)
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#define PCH_DEV_I2C7 _PCH_DEV(IEH, 1)
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#define PCH_DEV_IEH _PCH_DEV(IEH, 5)
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#define PCH_DEV_SLOT_SIO1 0x11
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#define PCH_DEVFN_UART3 _PCH_DEVFN(SIO1, 0)
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#define PCH_DEV_UART3 _PCH_DEV(SIO1, 0)
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#define PCH_DEV_SLOT_ISH 0x12
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#define PCH_DEVFN_ISH _PCH_DEVFN(ISH, 0)
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#define PCH_DEVFN_GSPI2 _PCH_DEVFN(ISH, 6)
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#define PCH_DEV_ISH _PCH_DEV(ISH, 0)
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#define PCH_DEV_GSPI2 _PCH_DEV(ISH, 6)
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#define PCH_DEV_SLOT_SIO2 0x13
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#define PCH_DEVFN_GSPI3 _PCH_DEVFN(SIO2, 0)
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#define PCH_DEV_GSPI3 _PCH_DEV(SIO2, 0)
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#define PCH_DEV_SLOT_SIO0 0x12
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#define PCH_DEVFN_GSPI2 _PCH_DEVFN(SIO0, 0)
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#define PCH_DEVFN_CSE_UMA _PCH_DEVFN(SIO0, 3)
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#define PCH_DEVFN_CSE_DMA _PCH_DEVFN(SIO0, 4)
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#define PCH_DEVFN_UFS0 _PCH_DEVFN(SIO0, 5)
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#define PCH_DEVFN_UFS1 _PCH_DEVFN(SIO0, 7)
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#define PCH_DEV_GSPI2 _PCH_DEV(SIO0, 0)
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#define PCH_DEV_CSE_UMA _PCH_DEV(SIO0, 3)
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#define PCH_DEV_CSE_DMA _PCH_DEV(SIO0, 4)
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#define PCH_DEV_UFS0 _PCH_DEV(SIO0, 5)
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#define PCH_DEV_UFS1 _PCH_DEV(SIO0, 7)
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#define PCH_DEV_SLOT_XHCI 0x14
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#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0)
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#define PCH_DEVFN_USBOTG _PCH_DEVFN(XHCI, 1)
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#define PCH_DEVFN_SRAM _PCH_DEVFN(XHCI, 2)
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#define PCH_DEVFN_CNVI_WIFI _PCH_DEVFN(XHCI, 3)
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#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0)
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#define PCH_DEV_USBOTG _PCH_DEV(XHCI, 1)
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#define PCH_DEV_SRAM _PCH_DEV(XHCI, 2)
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#define PCH_DEV_CNVI_WIFI _PCH_DEV(XHCI, 3)
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#define PCH_DEVFN_SDCARD _PCH_DEVFN(XHCI, 5)
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#define PCH_DEV_SDCARD _PCH_DEV(XHCI, 5)
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#define PCH_DEV_SLOT_SIO3 0x15
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#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO3, 0)
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#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO3, 1)
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#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO3, 2)
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#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO3, 3)
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#define PCH_DEV_I2C0 _PCH_DEV(SIO3, 0)
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#define PCH_DEV_I2C1 _PCH_DEV(SIO3, 1)
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#define PCH_DEV_I2C2 _PCH_DEV(SIO3, 2)
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#define PCH_DEV_I2C3 _PCH_DEV(SIO3, 3)
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#define PCH_DEV_SLOT_SIO1 0x15
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#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO1, 0)
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#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO1, 1)
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#define PCH_DEVFN_I2C2 _PCH_DEVFN(SIO1, 2)
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#define PCH_DEVFN_I2C3 _PCH_DEVFN(SIO1, 3)
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#define PCH_DEV_I2C0 _PCH_DEV(SIO1, 0)
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#define PCH_DEV_I2C1 _PCH_DEV(SIO1, 1)
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#define PCH_DEV_I2C2 _PCH_DEV(SIO1, 2)
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#define PCH_DEV_I2C3 _PCH_DEV(SIO1, 3)
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#define PCH_DEV_SLOT_CSE 0x16
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#define PCH_DEVFN_CSE _PCH_DEVFN(CSE, 0)
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#define PCH_DEVFN_CSE_2 _PCH_DEVFN(CSE, 1)
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#define PCH_DEVFN_CSE_IDER _PCH_DEVFN(CSE, 2)
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#define PCH_DEVFN_CSE_KT _PCH_DEVFN(CSE, 3)
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#define PCH_DEVFN_CSE_3 _PCH_DEVFN(CSE, 4)
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#define PCH_DEVFN_CSE_4 _PCH_DEVFN(CSE, 5)
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#define PCH_DEV_CSE _PCH_DEV(CSE, 0)
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#define PCH_DEV_CSE_2 _PCH_DEV(CSE, 1)
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#define PCH_DEV_CSE_IDER _PCH_DEV(CSE, 2)
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#define PCH_DEV_CSE_KT _PCH_DEV(CSE, 3)
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#define PCH_DEV_CSE_3 _PCH_DEV(CSE, 4)
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#define PCH_DEV_CSE_4 _PCH_DEV(CSE, 5)
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@ -107,17 +89,19 @@
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#define PCH_DEVFN_SATA _PCH_DEVFN(SATA, 0)
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#define PCH_DEV_SATA _PCH_DEV(SATA, 0)
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#define PCH_DEV_SLOT_SIO4 0x19
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#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO4, 0)
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#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO4, 1)
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#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO4, 2)
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#define PCH_DEV_I2C4 _PCH_DEV(SIO4, 0)
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#define PCH_DEV_I2C5 _PCH_DEV(SIO4, 1)
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#define PCH_DEV_UART2 _PCH_DEV(SIO4, 2)
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#define PCH_DEV_SLOT_SIO2 0x19
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#define PCH_DEVFN_I2C4 _PCH_DEVFN(SIO2, 0)
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#define PCH_DEVFN_I2C5 _PCH_DEVFN(SIO2, 1)
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#define PCH_DEVFN_UART2 _PCH_DEVFN(SIO2, 2)
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#define PCH_DEV_I2C4 _PCH_DEV(SIO2, 0)
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#define PCH_DEV_I2C5 _PCH_DEV(SIO2, 1)
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#define PCH_DEV_UART2 _PCH_DEV(SIO2, 2)
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#define PCH_DEV_SLOT_STORAGE 0x1a
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#define PCH_DEVFN_EMMC _PCH_DEVFN(STORAGE, 0)
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#define PCH_DEVFN_SDCARD _PCH_DEVFN(STORAGE, 1)
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#define PCH_DEV_EMMC _PCH_DEV(STORAGE, 0)
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#define PCH_DEV_SDCARD _PCH_DEV(STORAGE, 1)
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#define PCH_DEV_SLOT_PCIE 0x1c
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#define PCH_DEVFN_PCIE1 _PCH_DEVFN(PCIE, 0)
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@ -127,7 +111,6 @@
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#define PCH_DEVFN_PCIE5 _PCH_DEVFN(PCIE, 4)
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#define PCH_DEVFN_PCIE6 _PCH_DEVFN(PCIE, 5)
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#define PCH_DEVFN_PCIE7 _PCH_DEVFN(PCIE, 6)
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#define PCH_DEVFN_PCIE8 _PCH_DEVFN(PCIE, 7)
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#define PCH_DEV_PCIE1 _PCH_DEV(PCIE, 0)
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#define PCH_DEV_PCIE2 _PCH_DEV(PCIE, 1)
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#define PCH_DEV_PCIE3 _PCH_DEV(PCIE, 2)
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@ -135,27 +118,22 @@
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#define PCH_DEV_PCIE5 _PCH_DEV(PCIE, 4)
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#define PCH_DEV_PCIE6 _PCH_DEV(PCIE, 5)
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#define PCH_DEV_PCIE7 _PCH_DEV(PCIE, 6)
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#define PCH_DEV_PCIE8 _PCH_DEV(PCIE, 7)
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#define PCH_DEV_SLOT_PCIE_1 0x1d
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#define PCH_DEVFN_PCIE9 _PCH_DEVFN(PCIE_1, 0)
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#define PCH_DEVFN_PCIE10 _PCH_DEVFN(PCIE_1, 1)
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#define PCH_DEVFN_PCIE11 _PCH_DEVFN(PCIE_1, 2)
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#define PCH_DEVFN_PCIE12 _PCH_DEVFN(PCIE_1, 3)
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#define PCH_DEV_PCIE9 _PCH_DEV(PCIE_1, 0)
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#define PCH_DEV_PCIE10 _PCH_DEV(PCIE_1, 1)
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#define PCH_DEV_PCIE11 _PCH_DEV(PCIE_1, 2)
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#define PCH_DEV_PCIE12 _PCH_DEV(PCIE_1, 3)
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#define PCH_DEV_SLOT_SIO5 0x1e
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#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO5, 0)
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#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO5, 1)
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#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO5, 2)
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#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO5, 3)
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#define PCH_DEV_UART0 _PCH_DEV(SIO5, 0)
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#define PCH_DEV_UART1 _PCH_DEV(SIO5, 1)
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#define PCH_DEV_GSPI0 _PCH_DEV(SIO5, 2)
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#define PCH_DEV_GSPI1 _PCH_DEV(SIO5, 3)
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#define PCH_DEV_SLOT_SIO3 0x1e
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#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO3, 0)
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#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO3, 1)
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#define PCH_DEVFN_GSPI0 _PCH_DEVFN(SIO3, 2)
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#define PCH_DEVFN_GSPI1 _PCH_DEVFN(SIO3, 3)
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#define PCH_DEVFN_GBE _PCH_DEVFN(SIO3, 4)
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#define PCH_DEVFN_HPET _PCH_DEVFN(SIO3, 6)
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#define PCH_DEVFN_IOAPIC _PCH_DEVFN(SIO3, 7)
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#define PCH_DEV_UART0 _PCH_DEV(SIO3, 0)
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#define PCH_DEV_UART1 _PCH_DEV(SIO3, 1)
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#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2)
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#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3)
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#define PCH_DEV_GBE _PCH_DEV(SIO3, 4)
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#define PCH_DEV_HPET _PCH_DEV(SIO3, 6)
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#define PCH_DEV_IOAPIC _PCH_DEV(SIO3, 7)
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#define PCH_DEV_SLOT_ESPI 0x1f
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#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI
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@ -165,7 +143,6 @@
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#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3)
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#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4)
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#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5)
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#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6)
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#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7)
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#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0)
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#define PCH_DEV_LPC PCH_DEV_ESPI
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@ -186,7 +163,6 @@
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#define PCH_DEV_HDA _PCH_DEV(ESPI, 3)
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#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4)
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#define PCH_DEV_SPI _PCH_DEV(ESPI, 5)
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#define PCH_DEV_GBE _PCH_DEV(ESPI, 6)
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#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7)
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#endif
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