intel/i82801dx: Support 2MiB FWH part

Default setting of southbridge assigned 1MiB of memory
for FWH ID 0, while 2MiB is commercially available.
Only remap IDs when large ROM is requested in case some
board uses multiple FWH parts.

Change-Id: I500425f42f755f911d84c6f94a9f3ab5a1ca0b51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17918
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki 2016-12-04 15:39:44 +02:00
parent f2f4b78dd2
commit 3d0288d676
2 changed files with 25 additions and 0 deletions

View File

@ -29,4 +29,8 @@ config EHCI_BAR
hex
default 0xfef00000
config BOOTBLOCK_SOUTHBRIDGE_INIT
string
default "southbridge/intel/i82801dx/bootblock.c"
endif

View File

@ -0,0 +1,21 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
static void bootblock_southbridge_init(void)
{
/* Set FWH IDs for 2 MB flash part. */
if (CONFIG_ROM_SIZE == 0x200000)
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xe8, 0x00001111);
}