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mb/siemens/mc_ehl1: Adjust I2C bus enablement in devicetree 

This mainboard uses I2C1 and I2C4 buses only. Disable all the others as
they are not connected at all.

Change-Id: I4743f6ea6b9a9987ad63b60f56ee9a597a08284b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This commit is contained in:
Werner Zeh 2021-07-21 10:34:17 +02:00 committed by Patrick Georgi
parent 75178071fb
commit 3d0e10f230
1 changed files with 12 additions and 12 deletions
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24
src/mainboard/siemens/mc_ehl/variants/mc_ehl1/devicetree.cb
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@ -76,14 +76,14 @@ chip soc/intel/elkhartlake
# LPSS Serial IO (I2C/UART/GSPI) related UPDs
register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoDisabled,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C0] = PchSerialIoDisabled,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
[PchSerialIoIndexI2C4] = PchSerialIoPci,
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
[PchSerialIoIndexI2C6] = PchSerialIoPci,
[PchSerialIoIndexI2C7] = PchSerialIoPci,
[PchSerialIoIndexI2C6] = PchSerialIoDisabled,
[PchSerialIoIndexI2C7] = PchSerialIoDisabled,
}"
register "SerialIoI2cPadsTermination" = "{
@ -151,8 +151,8 @@ chip soc/intel/elkhartlake
device pci 08.0 off end # GNA
device pci 09.0 off end # CPU Intel Trace Hub
device pci 10.0 on end # I2C6
device pci 10.1 on end # I2C7
device pci 10.0 off end # I2C6
device pci 10.1 off end # I2C7
device pci 10.5 on end # Integrated Error Handler
device pci 11.0 off end # Intel PSE UART0
@ -180,10 +180,10 @@ chip soc/intel/elkhartlake
device pci 14.0 on end # USB3.1 xHCI
device pci 14.1 off end # USB3.1 xDCI (OTG)
device pci 15.0 on end # I2C0
device pci 15.0 off end # I2C0
device pci 15.1 on end # I2C1
device pci 15.2 on end # I2C2
device pci 15.3 on end # I2C3
device pci 15.2 off end # I2C2
device pci 15.3 off end # I2C3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 on end # Management Engine Interface 2
@ -201,7 +201,7 @@ chip soc/intel/elkhartlake
device pci 18.6 off end # Intel PSE QEP3
device pci 19.0 on end # I2C4
device pci 19.1 on end # I2C5
device pci 19.1 off end # I2C5
device pci 19.2 on end # UART2
device pci 1a.0 on end # eMMC