soc/intel/apollolake: Add NHLT table region to ACPI global nvs

Add address and length of NHLT table in ACPI.

Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/15025
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Saurabh Satija 2016-03-31 15:41:30 -07:00 committed by Aaron Durbin
parent cbaa2abd6f
commit 3d0e2871cb
2 changed files with 5 additions and 1 deletions

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@ -36,6 +36,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console CBMC, 32, // 0x05 - 0x08 - Coreboot Memory Console
PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index
GPEI, 64, // 0x11 - 0x18 - GPE Wake Source GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
NHLA, 64, // 0x19 - 0x20 - NHLT Address
NHLL, 32, // 0x21 - 0x24 - NHLT Length
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100), Offset (0x100),

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@ -36,7 +36,9 @@ struct global_nvs_t {
uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */ uint32_t cbmc; /* 0x05 - 0x08 - Coreboot Memory Console */
uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */
uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */
uint8_t unused[231]; uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */
uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */
uint8_t unused[219];
/* ChromeOS specific (0x100 - 0xfff) */ /* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos; chromeos_acpi_t chromeos;