soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS

As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI,
hence modify SoC code to reflect the same.

This patch replaces all SoC specific PCI LPC references with ESPI
except anything that touches intel common code block.

Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>

src/include/device/pci_ids.h

@@ -2723,13 +2723,13 @@
 #define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC	0x9d83
 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370	0xa306
 #define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370	0xa30c
-#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC	0x3480
+#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI	0x3480
-#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0	0x3481
+#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0	0x3481
-#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC	0x3482
+#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI	0x3482
-#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC		0x3483
+#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI	0x3483
-#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC		0x3484
+#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI	0x3484
-#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC	0x3487
+#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI	0x3487
-#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC	0x3486
+#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI	0x3486
 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC	0x0281
 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC	0x0283
 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC	0x0284

src/soc/intel/common/block/lpc/lpc.c

@@ -156,13 +156,13 @@ static const unsigned short pci_device_ids[] = {
 	PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
 	PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370,
 	PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370,
-	PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI,
-	PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI,
-	PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI,
-	PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI,
-	PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0,
+	PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0,
-	PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI,
-	PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC,
+	PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI,
 	PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC,
 	PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC,
 	PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC,

src/soc/intel/icelake/Makefile.inc

@@ -13,19 +13,19 @@ bootblock-y += bootblock/cpu.c
 bootblock-y += bootblock/pch.c
 bootblock-y += pmutil.c
 bootblock-y += bootblock/report_platform.c
+bootblock-y += espi.c
 bootblock-y += gpio.c
 bootblock-y += gspi.c
 bootblock-y += i2c.c
 bootblock-y += memmap.c
 bootblock-y += spi.c
-bootblock-y += lpc.c
 bootblock-y += p2sb.c
 bootblock-y += uart.c
 
+romstage-y += espi.c
 romstage-y += gpio.c
 romstage-y += gspi.c
 romstage-y += i2c.c
-romstage-y += lpc.c
 romstage-y += memmap.c
 romstage-y += pmutil.c
 romstage-y += reset.c
@@ -36,6 +36,7 @@ ramstage-y += acpi.c
 ramstage-y += chip.c
 ramstage-y += cpu.c
 ramstage-y += elog.c
+ramstage-y += espi.c
 ramstage-y += finalize.c
 ramstage-y += fsp_params.c
 ramstage-y += gpio.c
@@ -44,7 +45,6 @@ ramstage-y += gspi.c
 ramstage-y += gpio.c
 ramstage-y += i2c.c
 ramstage-y += lockdown.c
-ramstage-y += lpc.c
 ramstage-y += memmap.c
 ramstage-y += p2sb.c
 ramstage-y += pmc.c

src/soc/intel/icelake/acpi.c

@@ -169,7 +169,7 @@ void soc_power_states_generation(int core_id, int cores_per_package)
 void soc_fill_fadt(acpi_fadt_t *fadt)
 {
 	const uint16_t pmbase = ACPI_BASE_ADDRESS;
-	const struct device *dev = PCH_DEV_LPC;
+	const struct device *dev = pcidev_on_root(0, 0);
 	const struct soc_intel_icelake_config *config = dev->chip_info;
 
 	if (!config->PmTimerDisabled) {
@@ -194,7 +194,7 @@ uint32_t soc_read_sci_irq_select(void)
 
 void acpi_create_gnvs(struct global_nvs_t *gnvs)
 {
-	const struct device *dev = PCH_DEV_LPC;
+	const struct device *dev = pcidev_on_root(0, 0);
 	const struct soc_intel_icelake_config *config = dev->chip_info;
 
 	/* Set unknown wake source */

src/soc/intel/icelake/acpi/espi.asl

@@ -13,10 +13,12 @@
  * GNU General Public License for more details.
  */
 
+
+/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */
 Device (LPCB)
 {
 	Name (_ADR, 0x001f0000)
-	Name (_DDN, "LPC Bus Device")
+	Name (_DDN, "ESPI Bus Device")
 
 	Device (FWH)
 	{

src/soc/intel/icelake/acpi/southbridge.asl

@@ -32,8 +32,8 @@
 /* GPIO controller */
 #include "gpio.asl"
 
-/* LPC 0:1f.0 */
+/* ESPI 0:1f.0 */
-#include "lpc.asl"
+#include "espi.asl"
 
 /* PCH HDA */
 #include "pch_hda.asl"

src/soc/intel/icelake/bootblock/pch.c

@@ -26,8 +26,8 @@
 #include <intelblocks/smbus.h>
 #include <intelblocks/tco.h>
 #include <soc/bootblock.h>
+#include <soc/espi.h>
 #include <soc/iomap.h>
-#include <soc/lpc.h>
 #include <soc/p2sb.h>
 #include <soc/pch.h>
 #include <soc/pci_devs.h>
@@ -145,8 +145,8 @@ void pch_early_iorange_init(void)
 	if (pch_check_decode_enable() == 0) {
 		io_enables = lpc_enable_fixed_io_ranges(io_enables);
 		/*
-		 * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
+		 * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
-		 * value program in LPC PCI offset 82h.
+		 * value program in ESPI PCI offset 82h.
 		 */
 		pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
 	}

src/soc/intel/icelake/bootblock/report_platform.c

@@ -46,16 +46,16 @@ static struct {
 };
 
 static struct {
-	u16 lpcid;
+	u16 espiid;
 	const char *name;
 } pch_table[] = {
-	{ PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" },
+	{ PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" },
-	{ PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" },
+	{ PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" },
-	{ PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" },
+	{ PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" },
-	{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" },
+	{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" },
-	{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super REV0" },
+	{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" },
-	{ PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" },
+	{ PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" },
-	{ PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" },
+	{ PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" },
 };
 
 static struct {
@@ -170,18 +170,18 @@ static void report_mch_info(void)
 static void report_pch_info(void)
 {
 	int i;
-	pci_devfn_t dev = PCH_DEV_LPC;
+	pci_devfn_t dev = PCH_DEV_ESPI;
-	uint16_t lpcid = get_dev_id(dev);
+	uint16_t espiid = get_dev_id(dev);
 	const char *pch_type = "Unknown";
 
 	for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
-		if (pch_table[i].lpcid == lpcid) {
+		if (pch_table[i].espiid == espiid) {
 			pch_type = pch_table[i].name;
 			break;
 		}
 	}
 	printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
-		lpcid, get_dev_revision(dev), pch_type);
+		espiid, get_dev_revision(dev), pch_type);
 }
 
 static void report_igd_info(void)

src/soc/intel/icelake/chip.c

@@ -89,7 +89,8 @@ const char *soc_acpi_name(const struct device *dev)
 	case PCH_DEVFN_GSPI2:	return "SPI2";
 	case PCH_DEVFN_EMMC:	return "EMMC";
 	case PCH_DEVFN_SDCARD:	return "SDXC";
-	case PCH_DEVFN_LPC:	return "LPCB";
+	/* Keeping ACPI device name coherent with ec.asl */
+	case PCH_DEVFN_ESPI:	return "LPCB";
 	case PCH_DEVFN_P2SB:	return "P2SB";
 	case PCH_DEVFN_PMC:	return "PMC_";
 	case PCH_DEVFN_HDA:	return "HDAS";

src/soc/intel/icelake/espi.c

@@ -24,9 +24,9 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
 #include <reg_script.h>
+#include <soc/espi.h>
 #include <soc/iomap.h>
 #include <soc/irq.h>
-#include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pcr_ids.h>
 
@@ -71,10 +71,10 @@ uint8_t get_pch_series(void)
 	uint16_t lpc_did_hi_byte;
 
 	/*
-	 * Fetch upper 8 bits on LPC device ID to determine PCH type
+	 * Fetch upper 8 bits on ESPI device ID to determine PCH type
 	 * Adding 1 to the offset to fetch upper 8 bits
 	 */
-	lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1);
+	lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1);
 
 	if (lpc_did_hi_byte == 0x9D)
 		return PCH_LP;
@@ -87,11 +87,12 @@ uint8_t get_pch_series(void)
 #if ENV_RAMSTAGE
 static void soc_mirror_dmi_pcr_io_dec(void)
 {
+	struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0);
 	uint32_t io_dec_arr[] = {
-		pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC),
+		pci_read_config32(dev, ESPI_GEN1_DEC),
-		pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC),
+		pci_read_config32(dev, ESPI_GEN2_DEC),
-		pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC),
+		pci_read_config32(dev, ESPI_GEN3_DEC),
-		pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC),
+		pci_read_config32(dev, ESPI_GEN4_DEC),
 	};
 	/* Mirror these same settings in DMI PCR */
 	soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
@@ -215,10 +216,10 @@ void lpc_soc_init(struct device *dev)
 	isa_dma_init();
 	pch_misc_init();
 
-	/* Enable CLKRUN_EN for power gating LPC */
+	/* Enable CLKRUN_EN for power gating ESPI */
 	lpc_enable_pci_clk_cntl();
 
-	/* Set LPC Serial IRQ mode */
+	/* Set ESPI Serial IRQ mode */
 	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
 		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
 	else
@@ -233,13 +234,13 @@ void lpc_soc_init(struct device *dev)
 	soc_mirror_dmi_pcr_io_dec();
 }
 
-/* Fill up LPC IO resource structure inside SoC directory */
+/* Fill up ESPI IO resource structure inside SoC directory */
 void pch_lpc_soc_fill_io_resources(struct device *dev)
 {
 	/*
 	 * PMC pci device gets hidden from PCI bus due to Silicon
 	 * policy hence bind ACPI BASE aka ABASE (offset 0x20) with
-	 * LPC IO resources to ensure that ABASE falls under PCI reserved
+	 * ESPI IO resources to ensure that ABASE falls under PCI reserved
 	 * IO memory range.
 	 *
 	 * Note: Don't add any more resource with same offset 0x20

src/soc/intel/icelake/fsp_params.c

@@ -102,7 +102,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	}
 
 	/* Lan */
-	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 6);
+	dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
 	if (!dev)
 		params->PchLanEnable = 0;
 	else

src/soc/intel/icelake/include/soc/espi.h

@@ -13,12 +13,12 @@
  * GNU General Public License for more details.
  */
 
-#ifndef _SOC_ICELAKE_LPC_H_
+#ifndef _SOC_ICELAKE_ESPI_H_
-#define _SOC_ICELAKE_LPC_H_
+#define _SOC_ICELAKE_ESPI_H_
 
 #include <stdint.h>
 
-/* PCI Configuration Space (D31:F0): LPC */
+/* PCI Configuration Space (D31:F0): ESPI */
 #define SCI_IRQ_SEL		(7 << 0)
 #define SCIS_IRQ9		0
 #define SCIS_IRQ10		1
@@ -28,19 +28,14 @@
 #define SCIS_IRQ22		6
 #define SCIS_IRQ23		7
 #define SERIRQ_CNTL		0x64
-#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define ESPI_IO_DEC		0x80 /* IO Decode Ranges Register */
 #define   COMA_RANGE		0x0 /* 0x3F8 - 0x3FF COM1*/
 #define   COMB_RANGE		0x1 /* 0x2F8 - 0x2FF COM2*/
-#define LPC_EN			0x82 /* LPC IF Enables Register */
+#define ESPI_GEN1_DEC		0x84 /* ESPI IF Generic Decode Range 1 */
-#define LPC_GEN1_DEC		0x84 /* LPC IF Generic Decode Range 1 */
+#define ESPI_GEN2_DEC		0x88 /* ESPI IF Generic Decode Range 2 */
-#define LPC_GEN2_DEC		0x88 /* LPC IF Generic Decode Range 2 */
+#define ESPI_GEN3_DEC		0x8c /* ESPI IF Generic Decode Range 3 */
-#define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
+#define ESPI_GEN4_DEC		0x90 /* ESPI IF Generic Decode Range 4 */
-#define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
+#define LGMR			0x98 /* ESPI Generic Memory Range */
-#define LGMR			0x98 /* LPC Generic Memory Range */
-#define BIOS_CNTL		0xdc
-#define   LPC_BC_BILD		(1 << 7) /* BILD */
-#define   LPC_BC_LE		(1 << 1) /* LE */
-#define   LPC_BC_EISS		(1 << 5) /* EISS */
 #define PCCTL			0xE0 /* PCI Clock Control */
 #define   CLKRUN_EN		(1 << 0)
 

src/soc/intel/icelake/include/soc/pci_devs.h

@@ -171,22 +171,24 @@
 #define  PCH_DEV_GSPI0		_PCH_DEV(SIO3, 2)
 #define  PCH_DEV_GSPI1		_PCH_DEV(SIO3, 3)
 
-#define PCH_DEV_SLOT_LPC	0x1f
+#define PCH_DEV_SLOT_ESPI	0x1f
-#define  PCH_DEVFN_LPC		_PCH_DEVFN(LPC, 0)
+#define PCH_DEV_SLOT_LPC	PCH_DEV_SLOT_ESPI
-#define  PCH_DEVFN_P2SB		_PCH_DEVFN(LPC, 1)
+#define  PCH_DEVFN_ESPI		_PCH_DEVFN(ESPI, 0)
-#define  PCH_DEVFN_PMC		_PCH_DEVFN(LPC, 2)
+#define  PCH_DEVFN_P2SB		_PCH_DEVFN(ESPI, 1)
-#define  PCH_DEVFN_HDA		_PCH_DEVFN(LPC, 3)
+#define  PCH_DEVFN_PMC		_PCH_DEVFN(ESPI, 2)
-#define  PCH_DEVFN_SMBUS	_PCH_DEVFN(LPC, 4)
+#define  PCH_DEVFN_HDA		_PCH_DEVFN(ESPI, 3)
-#define  PCH_DEVFN_SPI		_PCH_DEVFN(LPC, 5)
+#define  PCH_DEVFN_SMBUS	_PCH_DEVFN(ESPI, 4)
-#define  PCH_DEVFN_GBE		_PCH_DEVFN(LPC, 6)
+#define  PCH_DEVFN_SPI		_PCH_DEVFN(ESPI, 5)
-#define  PCH_DEVFN_TRACEHUB	_PCH_DEVFN(LPC, 7)
+#define  PCH_DEVFN_GBE		_PCH_DEVFN(ESPI, 6)
-#define  PCH_DEV_LPC		_PCH_DEV(LPC, 0)
+#define  PCH_DEVFN_TRACEHUB	_PCH_DEVFN(ESPI, 7)
-#define  PCH_DEV_P2SB		_PCH_DEV(LPC, 1)
+#define  PCH_DEV_ESPI	_PCH_DEV(ESPI, 0)
-#define  PCH_DEV_PMC		_PCH_DEV(LPC, 2)
+#define  PCH_DEV_LPC		PCH_DEV_ESPI
-#define  PCH_DEV_HDA		_PCH_DEV(LPC, 3)
+#define  PCH_DEV_P2SB		_PCH_DEV(ESPI, 1)
-#define  PCH_DEV_SMBUS		_PCH_DEV(LPC, 4)
+#define  PCH_DEV_PMC		_PCH_DEV(ESPI, 2)
-#define  PCH_DEV_SPI		_PCH_DEV(LPC, 5)
+#define  PCH_DEV_HDA		_PCH_DEV(ESPI, 3)
-#define  PCH_DEV_GBE		_PCH_DEV(LPC, 6)
+#define  PCH_DEV_SMBUS		_PCH_DEV(ESPI, 4)
-#define  PCH_DEV_TRACEHUB	_PCH_DEV(LPC, 7)
+#define  PCH_DEV_SPI		_PCH_DEV(ESPI, 5)
+#define  PCH_DEV_GBE		_PCH_DEV(ESPI, 6)
+#define  PCH_DEV_TRACEHUB	_PCH_DEV(ESPI, 7)
 
 #endif

src/soc/intel/icelake/include/soc/pcr_ids.h

@@ -38,7 +38,7 @@
 #define PID_SCS		0xc0
 #define PID_RTC		0xc3
 #define PID_ITSS	0xc4
-#define PID_LPC		0xc7
+#define PID_ESPI	0xc7
 #define PID_SERIALIO	0xcb
 
 #endif

src/soc/intel/icelake/pmutil.c

@@ -30,10 +30,10 @@
 #include <intelblocks/rtc.h>
 #include <intelblocks/tco.h>
 #include <stdlib.h>
+#include <soc/espi.h>
 #include <soc/gpe.h>
 #include <soc/gpio.h>
 #include <soc/iomap.h>
-#include <soc/lpc.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
 #include <soc/smbus.h>