soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI, hence modify SoC code to reflect the same. This patch replaces all SoC specific PCI LPC references with ESPI except anything that touches intel common code block. Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
This commit is contained in:
Subrata Banik
parent
8a70918b8a
commit
3d152ac388
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@ -2723,13 +2723,13 @@
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#define PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC 0x9d83
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#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370 0xa306
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#define PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370 0xa30c
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#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC 0x3480
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#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0 0x3481
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#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC 0x3482
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#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC 0x3483
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#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC 0x3484
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#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC 0x3487
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#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC 0x3486
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#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI 0x3480
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#define PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0 0x3481
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#define PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI 0x3482
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#define PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI 0x3483
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#define PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI 0x3484
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#define PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI 0x3487
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#define PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI 0x3486
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#define PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC 0x0281
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#define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC 0x0283
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#define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284
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@ -156,13 +156,13 @@ static const unsigned short pci_device_ids[] = {
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PCI_DEVICE_ID_INTEL_CNL_Y_PREMIUM_LPC,
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PCI_DEVICE_ID_INTEL_CNP_H_LPC_Q370,
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PCI_DEVICE_ID_INTEL_CNP_H_LPC_QM370,
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PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC,
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PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC,
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PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC,
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PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC,
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PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0,
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PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC,
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PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC,
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PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI,
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PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI,
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PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI,
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PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI,
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PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0,
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PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI,
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PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI,
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PCI_DEVICE_ID_INTEL_CMP_SUPER_U_LPC,
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PCI_DEVICE_ID_INTEL_CMP_PREMIUM_Y_LPC,
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PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC,
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@ -13,19 +13,19 @@ bootblock-y += bootblock/cpu.c
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bootblock-y += bootblock/pch.c
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bootblock-y += pmutil.c
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bootblock-y += bootblock/report_platform.c
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bootblock-y += espi.c
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bootblock-y += gpio.c
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bootblock-y += gspi.c
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bootblock-y += i2c.c
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bootblock-y += memmap.c
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bootblock-y += spi.c
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bootblock-y += lpc.c
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bootblock-y += p2sb.c
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bootblock-y += uart.c
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romstage-y += espi.c
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romstage-y += gpio.c
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romstage-y += gspi.c
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romstage-y += i2c.c
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romstage-y += lpc.c
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romstage-y += memmap.c
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romstage-y += pmutil.c
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romstage-y += reset.c
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@ -36,6 +36,7 @@ ramstage-y += acpi.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-y += espi.c
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ramstage-y += finalize.c
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ramstage-y += fsp_params.c
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ramstage-y += gpio.c
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@ -44,7 +45,6 @@ ramstage-y += gspi.c
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ramstage-y += gpio.c
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ramstage-y += i2c.c
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ramstage-y += lockdown.c
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ramstage-y += lpc.c
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ramstage-y += memmap.c
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ramstage-y += p2sb.c
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ramstage-y += pmc.c
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@ -169,7 +169,7 @@ void soc_power_states_generation(int core_id, int cores_per_package)
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void soc_fill_fadt(acpi_fadt_t *fadt)
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{
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const uint16_t pmbase = ACPI_BASE_ADDRESS;
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const struct device *dev = PCH_DEV_LPC;
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const struct device *dev = pcidev_on_root(0, 0);
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const struct soc_intel_icelake_config *config = dev->chip_info;
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if (!config->PmTimerDisabled) {
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@ -194,7 +194,7 @@ uint32_t soc_read_sci_irq_select(void)
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void acpi_create_gnvs(struct global_nvs_t *gnvs)
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{
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const struct device *dev = PCH_DEV_LPC;
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const struct device *dev = pcidev_on_root(0, 0);
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const struct soc_intel_icelake_config *config = dev->chip_info;
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/* Set unknown wake source */
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@ -13,10 +13,12 @@
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* GNU General Public License for more details.
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*/
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/* Device identifier is not changed to ESPI to maintain coherency with ec.asl */
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Device (LPCB)
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{
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Name (_ADR, 0x001f0000)
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Name (_DDN, "LPC Bus Device")
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Name (_DDN, "ESPI Bus Device")
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Device (FWH)
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{
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@ -32,8 +32,8 @@
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/* GPIO controller */
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#include "gpio.asl"
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/* LPC 0:1f.0 */
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#include "lpc.asl"
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/* ESPI 0:1f.0 */
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#include "espi.asl"
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/* PCH HDA */
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#include "pch_hda.asl"
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@ -26,8 +26,8 @@
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#include <intelblocks/smbus.h>
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#include <intelblocks/tco.h>
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#include <soc/bootblock.h>
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#include <soc/espi.h>
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#include <soc/iomap.h>
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#include <soc/lpc.h>
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#include <soc/p2sb.h>
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#include <soc/pch.h>
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#include <soc/pci_devs.h>
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@ -145,8 +145,8 @@ void pch_early_iorange_init(void)
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if (pch_check_decode_enable() == 0) {
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io_enables = lpc_enable_fixed_io_ranges(io_enables);
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/*
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* Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same
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* value program in LPC PCI offset 82h.
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* Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same
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* value program in ESPI PCI offset 82h.
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*/
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pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables);
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}
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@ -46,16 +46,16 @@ static struct {
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};
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static struct {
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u16 lpcid;
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u16 espiid;
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const char *name;
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} pch_table[] = {
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{ PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" },
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{ PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" },
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{ PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" },
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{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" },
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{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super REV0" },
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{ PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" },
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{ PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" },
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{ PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" },
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{ PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" },
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{ PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" },
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{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" },
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{ PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" },
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{ PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" },
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{ PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" },
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};
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static struct {
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@ -170,18 +170,18 @@ static void report_mch_info(void)
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static void report_pch_info(void)
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{
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int i;
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pci_devfn_t dev = PCH_DEV_LPC;
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uint16_t lpcid = get_dev_id(dev);
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pci_devfn_t dev = PCH_DEV_ESPI;
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uint16_t espiid = get_dev_id(dev);
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const char *pch_type = "Unknown";
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for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
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if (pch_table[i].lpcid == lpcid) {
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if (pch_table[i].espiid == espiid) {
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pch_type = pch_table[i].name;
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break;
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}
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}
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printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n",
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lpcid, get_dev_revision(dev), pch_type);
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espiid, get_dev_revision(dev), pch_type);
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}
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static void report_igd_info(void)
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@ -89,7 +89,8 @@ const char *soc_acpi_name(const struct device *dev)
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case PCH_DEVFN_GSPI2: return "SPI2";
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case PCH_DEVFN_EMMC: return "EMMC";
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case PCH_DEVFN_SDCARD: return "SDXC";
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case PCH_DEVFN_LPC: return "LPCB";
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/* Keeping ACPI device name coherent with ec.asl */
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case PCH_DEVFN_ESPI: return "LPCB";
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case PCH_DEVFN_P2SB: return "P2SB";
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case PCH_DEVFN_PMC: return "PMC_";
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case PCH_DEVFN_HDA: return "HDAS";
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@ -24,9 +24,9 @@
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/pcr.h>
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#include <reg_script.h>
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#include <soc/espi.h>
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#include <soc/iomap.h>
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#include <soc/irq.h>
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#include <soc/lpc.h>
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#include <soc/pci_devs.h>
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#include <soc/pcr_ids.h>
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@ -71,10 +71,10 @@ uint8_t get_pch_series(void)
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uint16_t lpc_did_hi_byte;
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/*
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* Fetch upper 8 bits on LPC device ID to determine PCH type
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* Fetch upper 8 bits on ESPI device ID to determine PCH type
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* Adding 1 to the offset to fetch upper 8 bits
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*/
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lpc_did_hi_byte = pci_read_config8(PCH_DEV_LPC, PCI_DEVICE_ID + 1);
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lpc_did_hi_byte = pci_read_config8(PCH_DEV_ESPI, PCI_DEVICE_ID + 1);
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if (lpc_did_hi_byte == 0x9D)
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return PCH_LP;
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@ -87,11 +87,12 @@ uint8_t get_pch_series(void)
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#if ENV_RAMSTAGE
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static void soc_mirror_dmi_pcr_io_dec(void)
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{
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struct device *dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 0);
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uint32_t io_dec_arr[] = {
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pci_read_config32(PCH_DEV_LPC, LPC_GEN1_DEC),
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pci_read_config32(PCH_DEV_LPC, LPC_GEN2_DEC),
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pci_read_config32(PCH_DEV_LPC, LPC_GEN3_DEC),
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pci_read_config32(PCH_DEV_LPC, LPC_GEN4_DEC),
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pci_read_config32(dev, ESPI_GEN1_DEC),
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pci_read_config32(dev, ESPI_GEN2_DEC),
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pci_read_config32(dev, ESPI_GEN3_DEC),
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pci_read_config32(dev, ESPI_GEN4_DEC),
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};
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/* Mirror these same settings in DMI PCR */
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soc_setup_dmi_pcr_io_dec(&io_dec_arr[0]);
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@ -215,10 +216,10 @@ void lpc_soc_init(struct device *dev)
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isa_dma_init();
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pch_misc_init();
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/* Enable CLKRUN_EN for power gating LPC */
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/* Enable CLKRUN_EN for power gating ESPI */
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lpc_enable_pci_clk_cntl();
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/* Set LPC Serial IRQ mode */
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/* Set ESPI Serial IRQ mode */
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if (CONFIG(SERIRQ_CONTINUOUS_MODE))
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lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
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else
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@ -233,13 +234,13 @@ void lpc_soc_init(struct device *dev)
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soc_mirror_dmi_pcr_io_dec();
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}
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/* Fill up LPC IO resource structure inside SoC directory */
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/* Fill up ESPI IO resource structure inside SoC directory */
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void pch_lpc_soc_fill_io_resources(struct device *dev)
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{
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/*
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* PMC pci device gets hidden from PCI bus due to Silicon
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* policy hence bind ACPI BASE aka ABASE (offset 0x20) with
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* LPC IO resources to ensure that ABASE falls under PCI reserved
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* ESPI IO resources to ensure that ABASE falls under PCI reserved
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* IO memory range.
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*
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* Note: Don't add any more resource with same offset 0x20
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@ -102,7 +102,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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}
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/* Lan */
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dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 6);
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dev = pcidev_on_root(PCH_DEV_SLOT_ESPI, 6);
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if (!dev)
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params->PchLanEnable = 0;
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else
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@ -13,12 +13,12 @@
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* GNU General Public License for more details.
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*/
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#ifndef _SOC_ICELAKE_LPC_H_
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#define _SOC_ICELAKE_LPC_H_
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#ifndef _SOC_ICELAKE_ESPI_H_
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#define _SOC_ICELAKE_ESPI_H_
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#include <stdint.h>
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/* PCI Configuration Space (D31:F0): LPC */
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/* PCI Configuration Space (D31:F0): ESPI */
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#define SCI_IRQ_SEL (7 << 0)
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#define SCIS_IRQ9 0
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#define SCIS_IRQ10 1
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@ -28,19 +28,14 @@
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#define SCIS_IRQ22 6
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#define SCIS_IRQ23 7
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#define SERIRQ_CNTL 0x64
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
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#define ESPI_IO_DEC 0x80 /* IO Decode Ranges Register */
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#define COMA_RANGE 0x0 /* 0x3F8 - 0x3FF COM1*/
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#define COMB_RANGE 0x1 /* 0x2F8 - 0x2FF COM2*/
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#define LPC_EN 0x82 /* LPC IF Enables Register */
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#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
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#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
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#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
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#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
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#define LGMR 0x98 /* LPC Generic Memory Range */
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#define BIOS_CNTL 0xdc
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#define LPC_BC_BILD (1 << 7) /* BILD */
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#define LPC_BC_LE (1 << 1) /* LE */
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#define LPC_BC_EISS (1 << 5) /* EISS */
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#define ESPI_GEN1_DEC 0x84 /* ESPI IF Generic Decode Range 1 */
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#define ESPI_GEN2_DEC 0x88 /* ESPI IF Generic Decode Range 2 */
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#define ESPI_GEN3_DEC 0x8c /* ESPI IF Generic Decode Range 3 */
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#define ESPI_GEN4_DEC 0x90 /* ESPI IF Generic Decode Range 4 */
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#define LGMR 0x98 /* ESPI Generic Memory Range */
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#define PCCTL 0xE0 /* PCI Clock Control */
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#define CLKRUN_EN (1 << 0)
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@ -171,22 +171,24 @@
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#define PCH_DEV_GSPI0 _PCH_DEV(SIO3, 2)
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#define PCH_DEV_GSPI1 _PCH_DEV(SIO3, 3)
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#define PCH_DEV_SLOT_LPC 0x1f
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#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0)
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#define PCH_DEVFN_P2SB _PCH_DEVFN(LPC, 1)
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#define PCH_DEVFN_PMC _PCH_DEVFN(LPC, 2)
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#define PCH_DEVFN_HDA _PCH_DEVFN(LPC, 3)
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#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 4)
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#define PCH_DEVFN_SPI _PCH_DEVFN(LPC, 5)
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#define PCH_DEVFN_GBE _PCH_DEVFN(LPC, 6)
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#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(LPC, 7)
|
||||
#define PCH_DEV_LPC _PCH_DEV(LPC, 0)
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||||
#define PCH_DEV_P2SB _PCH_DEV(LPC, 1)
|
||||
#define PCH_DEV_PMC _PCH_DEV(LPC, 2)
|
||||
#define PCH_DEV_HDA _PCH_DEV(LPC, 3)
|
||||
#define PCH_DEV_SMBUS _PCH_DEV(LPC, 4)
|
||||
#define PCH_DEV_SPI _PCH_DEV(LPC, 5)
|
||||
#define PCH_DEV_GBE _PCH_DEV(LPC, 6)
|
||||
#define PCH_DEV_TRACEHUB _PCH_DEV(LPC, 7)
|
||||
#define PCH_DEV_SLOT_ESPI 0x1f
|
||||
#define PCH_DEV_SLOT_LPC PCH_DEV_SLOT_ESPI
|
||||
#define PCH_DEVFN_ESPI _PCH_DEVFN(ESPI, 0)
|
||||
#define PCH_DEVFN_P2SB _PCH_DEVFN(ESPI, 1)
|
||||
#define PCH_DEVFN_PMC _PCH_DEVFN(ESPI, 2)
|
||||
#define PCH_DEVFN_HDA _PCH_DEVFN(ESPI, 3)
|
||||
#define PCH_DEVFN_SMBUS _PCH_DEVFN(ESPI, 4)
|
||||
#define PCH_DEVFN_SPI _PCH_DEVFN(ESPI, 5)
|
||||
#define PCH_DEVFN_GBE _PCH_DEVFN(ESPI, 6)
|
||||
#define PCH_DEVFN_TRACEHUB _PCH_DEVFN(ESPI, 7)
|
||||
#define PCH_DEV_ESPI _PCH_DEV(ESPI, 0)
|
||||
#define PCH_DEV_LPC PCH_DEV_ESPI
|
||||
#define PCH_DEV_P2SB _PCH_DEV(ESPI, 1)
|
||||
#define PCH_DEV_PMC _PCH_DEV(ESPI, 2)
|
||||
#define PCH_DEV_HDA _PCH_DEV(ESPI, 3)
|
||||
#define PCH_DEV_SMBUS _PCH_DEV(ESPI, 4)
|
||||
#define PCH_DEV_SPI _PCH_DEV(ESPI, 5)
|
||||
#define PCH_DEV_GBE _PCH_DEV(ESPI, 6)
|
||||
#define PCH_DEV_TRACEHUB _PCH_DEV(ESPI, 7)
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@
|
|||
#define PID_SCS 0xc0
|
||||
#define PID_RTC 0xc3
|
||||
#define PID_ITSS 0xc4
|
||||
#define PID_LPC 0xc7
|
||||
#define PID_ESPI 0xc7
|
||||
#define PID_SERIALIO 0xcb
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -30,10 +30,10 @@
|
|||
#include <intelblocks/rtc.h>
|
||||
#include <intelblocks/tco.h>
|
||||
#include <stdlib.h>
|
||||
#include <soc/espi.h>
|
||||
#include <soc/gpe.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/iomap.h>
|
||||
#include <soc/lpc.h>
|
||||
#include <soc/pci_devs.h>
|
||||
#include <soc/pm.h>
|
||||
#include <soc/smbus.h>
|
||||
|
|
|
|||
Loading…
Reference in New Issue