mb/google/poppy/variants/rammus: add memory configuration
Add memory configuration based on the proto board schematics BUG=b:111579386 BRANCH=Master TEST=Build pass Change-Id: I45efdc7893b5bcbca0de6e932e1452cc1a2ff028 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/27806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -1,2 +1,5 @@
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SPD_SOURCES = empty # 0b0000
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SPD_SOURCES = empty # 0b0000
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romstage-y += memory.c
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ramstage-y += nhlt.c
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ramstage-y += nhlt.c
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@ -0,0 +1,49 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2018 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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/* DQ byte map */
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static const u8 dq_map[][12] = {
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{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
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0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
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{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
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0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 }
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};
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/* DQS CPU<>DRAM map */
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static const u8 dqs_map[][8] = {
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{ 0, 1, 3, 2, 4, 5, 6, 7 },
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{ 1, 0, 4, 5, 2, 3, 6, 7 },
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};
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/* Rcomp resistor */
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static const u16 rcomp_resistor[] = { 200, 81, 162 };
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/* Rcomp target */
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static const u16 rcomp_target[] = { 100, 40, 40, 23, 40 };
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void variant_memory_params(struct memory_params *p)
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{
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p->type = MEMORY_LPDDR3;
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p->dq_map = dq_map;
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p->dq_map_size = sizeof(dq_map);
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p->dqs_map = dqs_map;
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p->dqs_map_size = sizeof(dqs_map);
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p->rcomp_resistor = rcomp_resistor;
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p->rcomp_resistor_size = sizeof(rcomp_resistor);
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p->rcomp_target = rcomp_target;
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p->rcomp_target_size = sizeof(rcomp_target);
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}
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