soc/amd: unify SMBus support
The SMBus support is identical between stoneyridge and picasso. Unify on common support code. Change-Id: Ic3412c5ee67977a45c50b68f36acc45c3d560db5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38616 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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@ -0,0 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_SMBUS
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bool
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default n
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help
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Select this option to add FCH SMBus controller functions to the build.
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@ -0,0 +1,7 @@
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS),y)
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romstage-y += smbus.c
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ramstage-y += smbus.c
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ramstage-y += sm.c
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endif
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@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_HDA
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select SOC_AMD_COMMON_BLOCK_SATA
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select SOC_AMD_COMMON_BLOCK_SMBUS
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select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select PARALLEL_MP
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@ -41,7 +41,6 @@ romstage-y += i2c.c
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romstage-y += romstage.c
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romstage-y += gpio.c
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romstage-y += pmutil.c
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romstage-y += smbus.c
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romstage-y += memmap.c
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romstage-$(CONFIG_PICASSO_UART) += uart.c
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romstage-y += tsc_freq.c
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@ -71,8 +70,6 @@ ramstage-y += northbridge.c
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ramstage-y += pmutil.c
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ramstage-y += acp.c
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ramstage-y += sata.c
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ramstage-y += sm.c
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ramstage-y += smbus.c
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ramstage-y += memmap.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
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@ -1,103 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <device/smbus.h>
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#include <device/smbus_host.h>
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#include <cpu/x86/lapic.h>
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#include <arch/ioapic.h>
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#include <soc/southbridge.h>
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/*
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* The southbridge enables all USB controllers by default in SMBUS Control.
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* The southbridge enables SATA by default in SMBUS Control.
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*/
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static void sm_init(struct device *dev)
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{
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setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS);
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}
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static u32 get_sm_mmio(struct device *dev)
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{
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struct resource *res;
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struct bus *pbus;
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pbus = get_pbus_smbus(dev);
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res = find_resource(pbus->dev, 0x90);
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if (res->base == SMB_BASE_ADDR)
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return ACPIMMIO_SMBUS_BASE;
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return ACPIMMIO_ASF_BASE;
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}
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static int lsmbus_recv_byte(struct device *dev)
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{
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u8 device;
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device = dev->path.i2c.device;
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return do_smbus_recv_byte(get_sm_mmio(dev), device);
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}
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static int lsmbus_send_byte(struct device *dev, u8 val)
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{
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u8 device;
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device = dev->path.i2c.device;
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return do_smbus_send_byte(get_sm_mmio(dev), device, val);
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}
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static int lsmbus_read_byte(struct device *dev, u8 address)
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{
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u8 device;
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device = dev->path.i2c.device;
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return do_smbus_read_byte(get_sm_mmio(dev), device, address);
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}
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static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
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{
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u8 device;
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device = dev->path.i2c.device;
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return do_smbus_write_byte(get_sm_mmio(dev), device, address, val);
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}
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static struct smbus_bus_operations lops_smbus_bus = {
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.recv_byte = lsmbus_recv_byte,
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.send_byte = lsmbus_send_byte,
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.read_byte = lsmbus_read_byte,
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.write_byte = lsmbus_write_byte,
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};
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static struct pci_operations lops_pci = {
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.set_subsystem = pci_dev_set_subsystem,
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};
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static struct device_operations smbus_ops = {
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.read_resources = DEVICE_NOOP,
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.set_resources = DEVICE_NOOP,
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.enable_resources = pci_dev_enable_resources,
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.init = sm_init,
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.scan_bus = scan_smbus,
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.ops_pci = &lops_pci,
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.ops_smbus_bus = &lops_smbus_bus,
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};
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static const struct pci_driver smbus_driver __pci_driver = {
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.ops = &smbus_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_CZ_SMBUS,
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};
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@ -51,6 +51,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_AMD_COMMON_BLOCK_PSP
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select SOC_AMD_COMMON_BLOCK_CAR
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select SOC_AMD_COMMON_BLOCK_S3
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select SOC_AMD_COMMON_BLOCK_SMBUS
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select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
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select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH
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select PARALLEL_MP
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@ -56,7 +56,6 @@ romstage-y += enable_usbdebug.c
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romstage-y += gpio.c
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romstage-y += monotonic_timer.c
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romstage-y += pmutil.c
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romstage-y += smbus.c
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romstage-y += smbus_spd.c
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romstage-y += memmap.c
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romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
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@ -90,8 +89,6 @@ ramstage-y += southbridge.c
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ramstage-y += northbridge.c
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ramstage-y += pmutil.c
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ramstage-y += sata.c
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ramstage-y += sm.c
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ramstage-y += smbus.c
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ramstage-y += memmap.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
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@ -1,196 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <stdint.h>
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#include <console/console.h>
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#include <device/smbus_host.h>
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#include <amdblocks/acpimmio.h>
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#include <soc/southbridge.h>
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/*
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* Between 1-10 seconds, We should never timeout normally
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* Longer than this is just painful when a timeout condition occurs.
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*/
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#define SMBUS_TIMEOUT (100 * 1000 * 10)
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static u8 controller_read8(uintptr_t base, u8 reg)
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{
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switch (base) {
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case ACPIMMIO_SMBUS_BASE:
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return smbus_read8(reg);
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case ACPIMMIO_ASF_BASE:
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return asf_read8(reg);
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default:
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printk(BIOS_ERR, "Error attempting to read SMBus at address 0x%lx\n",
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base);
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}
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return 0xff;
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}
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static void controller_write8(uintptr_t base, u8 reg, u8 val)
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{
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switch (base) {
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case ACPIMMIO_SMBUS_BASE:
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smbus_write8(reg, val);
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break;
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case ACPIMMIO_ASF_BASE:
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asf_write8(reg, val);
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break;
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default:
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printk(BIOS_ERR, "Error attempting to write SMBus at address 0x%lx\n",
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base);
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}
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}
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static int smbus_wait_until_ready(uintptr_t mmio)
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{
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u32 loops;
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loops = SMBUS_TIMEOUT;
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do {
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u8 val;
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val = controller_read8(mmio, SMBHSTSTAT);
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val &= SMBHST_STAT_VAL_BITS;
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if (val == 0) { /* ready now */
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return 0;
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}
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controller_write8(mmio, SMBHSTSTAT, val);
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} while (--loops);
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return -2; /* time out */
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}
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static int smbus_wait_until_done(uintptr_t mmio)
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{
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u32 loops;
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loops = SMBUS_TIMEOUT;
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do {
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u8 val;
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val = controller_read8(mmio, SMBHSTSTAT);
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val &= SMBHST_STAT_VAL_BITS; /* mask off reserved bits */
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if (val & SMBHST_STAT_ERROR_BITS)
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return -5; /* error */
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if (val == SMBHST_STAT_NOERROR) {
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controller_write8(mmio, SMBHSTSTAT, val); /* clr sts */
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return 0;
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}
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} while (--loops);
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return -3; /* timeout */
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}
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int do_smbus_recv_byte(uintptr_t mmio, u8 device)
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{
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u8 byte;
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if (smbus_wait_until_ready(mmio) < 0)
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return -2; /* not ready */
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/* set the device I'm talking to */
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controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
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byte = controller_read8(mmio, SMBHSTCTRL);
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byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
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byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */
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controller_write8(mmio, SMBHSTCTRL, byte);
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/* poll for transaction completion */
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if (smbus_wait_until_done(mmio) < 0)
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return -3; /* timeout or error */
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/* read results of transaction */
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byte = controller_read8(mmio, SMBHSTDAT0);
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return byte;
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}
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int do_smbus_send_byte(uintptr_t mmio, u8 device, u8 val)
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{
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u8 byte;
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if (smbus_wait_until_ready(mmio) < 0)
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return -2; /* not ready */
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/* set the command... */
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controller_write8(mmio, SMBHSTDAT0, val);
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/* set the device I'm talking to */
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controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
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byte = controller_read8(mmio, SMBHSTCTRL);
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byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
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byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BTE_RW; /* set mode, start */
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controller_write8(mmio, SMBHSTCTRL, byte);
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/* poll for transaction completion */
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if (smbus_wait_until_done(mmio) < 0)
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return -3; /* timeout or error */
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return 0;
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}
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int do_smbus_read_byte(uintptr_t mmio, u8 device, u8 address)
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{
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u8 byte;
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if (smbus_wait_until_ready(mmio) < 0)
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return -2; /* not ready */
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/* set the command/address... */
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controller_write8(mmio, SMBHSTCMD, address & 0xff);
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/* set the device I'm talking to */
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controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 1);
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byte = controller_read8(mmio, SMBHSTCTRL);
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byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
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byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */
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controller_write8(mmio, SMBHSTCTRL, byte);
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/* poll for transaction completion */
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if (smbus_wait_until_done(mmio) < 0)
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return -3; /* timeout or error */
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/* read results of transaction */
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byte = controller_read8(mmio, SMBHSTDAT0);
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return byte;
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}
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int do_smbus_write_byte(uintptr_t mmio, u8 device, u8 address, u8 val)
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{
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u8 byte;
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if (smbus_wait_until_ready(mmio) < 0)
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return -2; /* not ready */
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/* set the command/address... */
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controller_write8(mmio, SMBHSTCMD, address & 0xff);
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/* set the device I'm talking to */
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controller_write8(mmio, SMBHSTADDR, ((device & 0x7f) << 1) | 0);
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/* output value */
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controller_write8(mmio, SMBHSTDAT0, val);
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byte = controller_read8(mmio, SMBHSTCTRL);
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byte &= ~SMBHST_CTRL_MODE_BITS; /* Clear [4:2] */
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byte |= SMBHST_CTRL_STRT | SMBHST_CTRL_BDT_RW; /* set mode, start */
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controller_write8(mmio, SMBHSTCTRL, byte);
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/* poll for transaction completion */
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if (smbus_wait_until_done(mmio) < 0)
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return -3; /* timeout or error */
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return 0;
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}
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