From 3d302b03f46fa6ed5927cdc2ef9f53b9ce0262ae Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Sat, 12 Nov 2016 07:31:16 -0800 Subject: [PATCH] riscv: add a variable to control trap management MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This variable can be set in a debugger (e.g. Spike) to finely control which traps go to coreboot and which go to the supervisor. Change-Id: I292264c15f002c41cf8d278354d8f4c0efbd0895 Signed-off-by: Ronald G. Minnich Reviewed-on: https://review.coreboot.org/17404 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer --- src/arch/riscv/virtual_memory.c | 26 ++++++++++++++++---------- 1 file changed, 16 insertions(+), 10 deletions(-) diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index 999d73cec8..6d93bd0def 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -23,6 +23,21 @@ #include #include +/* Delegate controls which traps are delegated to the payload. If you + * wish to temporarily disable some or all delegation you can, in a + * debugger, set it to a different value (e.g. 0 to have all traps go + * to M-mode). In practice, this variable has been a lifesaver. It is + * still not quite determined which delegation might by unallowed by + * the spec so for now we enumerate and set them all. */ +static int delegate = 0 + | (1 << CAUSE_MISALIGNED_FETCH) + | (1 << CAUSE_FAULT_FETCH) + | (1 << CAUSE_ILLEGAL_INSTRUCTION) + | (1 << CAUSE_BREAKPOINT) + | (1 << CAUSE_FAULT_LOAD) + | (1 << CAUSE_FAULT_STORE) + | (1 << CAUSE_USER_ECALL) + ; pte_t* root_page_table; /* Indent the following text by 2*level spaces */ @@ -223,16 +238,7 @@ void mstatus_init(void) clear_csr(mip, MIP_MSIP); set_csr(mie, MIP_MSIP); - /* Configure which exception causes are delegated to supervisor mode */ - set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH) - | (1 << CAUSE_FAULT_FETCH) - | (1 << CAUSE_ILLEGAL_INSTRUCTION) - | (1 << CAUSE_BREAKPOINT) - | (1 << CAUSE_FAULT_LOAD) - | (1 << CAUSE_FAULT_STORE) - | (1 << CAUSE_USER_ECALL) - ); - + set_csr(medeleg, delegate); /* Enable all user/supervisor-mode counters */ /* We'll turn these on once lowrisc gets their bitstream up to