google/cyan: Use GpioInt for Keyboard IRQ

Cherry-pick from Chromium commit a162348.

Remove the hard coded IRQ number for the keyboard interrupt.
IRQ number can change based upon the gpio bank index ordering.
Hence pass the gpio bank and index number so that kernel calculates
the IRQ number.

Original-Change-Id: Icfe5c3995007164bf617575b541758c18ee63a1d
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I81ff19e3060c533ee76023c7651f741294e9db30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/google/cyan/acpi/superio.asl

@@ -23,8 +23,8 @@
 #define SIO_EC_ENABLE_PS2K       /* Enable PS/2 Keyboard */
 
 /* Override default IRQ settings */
-#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow){\
-                                                     BOARD_I8042_IRQ}
+#define SIO_EC_PS2K_IRQ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,,\
+				 "\\_SB.GPNC") { BOARD_I8042_GPIO_INDEX }
 
 /* ACPI code for EC SuperIO functions */
 #include <ec/google/chromeec/acpi/superio.asl>

src/mainboard/google/cyan/onboard.h

@@ -30,16 +30,11 @@
  * GPSE_SIZE = 86
  */
 
-/*
- * gpio based irq for kbd, 17th index in North Bank
- * MAX_DIRECT_IRQ + GPSW_SIZE + 18
- */
-/* ToDO: change kbd irq to gpio bank index */
-#define BOARD_I8042_IRQ			182
 #define BOARD_TOUCH_IRQ			184
 #define BOARD_PRE_EVT_TOUCH_IRQ		156
 
-
+/* KBD: Gpio index in N bank */
+#define BOARD_I8042_GPIO_INDEX		17
 /* SCI: Gpio index in N bank */
 #define BOARD_SCI_GPIO_INDEX		15
 /* Trackpad: Gpio index in N bank */