mb/google/drallion: Correct GPP_E7 as stop pin
Current design reset pin is connected to PLTRST. GPP_E7 is stop pin for touch. Reserve reset pin for next stage implement. BUG=b:143733039 BRANCH=N/A TEST=check touch screen can work properly Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3ebd56ab49b87da425583da04f082e69293a023e Reviewed-on: https://review.coreboot.org/c/coreboot/+/36535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
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@ -322,8 +322,8 @@ chip soc/intel/cannonlake
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register "generic.desc" = ""Wacom Touchscreen""
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register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
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register "generic.reset_delay_ms" = "20"
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register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
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register "generic.stop_delay_ms" = "20"
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register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
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register "generic.enable_delay_ms" = "55"
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register "generic.has_power_resource" = "1"
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@ -338,9 +338,9 @@ chip soc/intel/cannonlake
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register "generic.desc" = ""ELAN Touchscreen""
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register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)"
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register "generic.probed" = "1"
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register "generic.reset_gpio" =
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register "generic.stop_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
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register "generic.reset_delay_ms" = "10"
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register "generic.stop_delay_ms" = "10"
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register "generic.enable_gpio" =
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"ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
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register "generic.enable_delay_ms" = "55"
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@ -355,8 +355,8 @@ chip soc/intel/cannonlake
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register "desc" = ""Melfas Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
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register "reset_delay_ms" = "10"
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"
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register "stop_delay_ms" = "10"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)"
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register "enable_delay_ms" = "55"
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register "has_power_resource" = "1"
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