From 3d4fbf763f09924b219b3bbf70c2a8a6532c4c80 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Thu, 18 Jan 2024 01:12:16 +0100 Subject: [PATCH] mb/siemens/chili: Use chipset dt reference names Use the references from the chipset devicetree as this makes the comments superfluous. Change-Id: Ic3a4c85ec6bfdc858f9b6f79b114cf612ad3a153 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/80022 Reviewed-by: Eric Lai Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../siemens/chili/variants/base/devicetree.cb | 136 ++++++++--------- .../chili/variants/chili/devicetree.cb | 140 +++++++++--------- 2 files changed, 138 insertions(+), 138 deletions(-) diff --git a/src/mainboard/siemens/chili/variants/base/devicetree.cb b/src/mainboard/siemens/chili/variants/base/devicetree.cb index 8d6c589e4a..4bc9b5f007 100644 --- a/src/mainboard/siemens/chili/variants/base/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/base/devicetree.cb @@ -10,19 +10,19 @@ chip soc/intel/cannonlake device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 01.0 off end # PCIe x16 - device pci 01.1 off end # PCIe x8 - device pci 01.2 off end # PCIe x4 - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 05.0 off end # Imaging Processing Unit - device pci 08.0 off end # Gaussian mixture model, Neural network accelerator - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # ISH - device pci 14.0 on # USB xHCI + device ref system_agent on end + device ref peg0 off end + device ref peg1 off end + device ref peg2 off end + device ref igpu on end + device ref dptf on end + device ref ipu off end + device ref gna off end + device ref thermal on end + device ref ufs off end + device ref gspi2 off end + device ref ish off end + device ref xhci on # USB2 register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC2)" # Type-C? register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # single blue @@ -37,21 +37,21 @@ chip soc/intel/cannonlake register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Realtek storage? register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC0)" # single blue end - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Shared SRAM - device pci 14.3 off end # CNVi Wifi - device pci 14.5 off end # SDCard - device pci 15.0 off end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 on # SATA + device ref xdci off end + device ref shared_sram on end + device ref cnvi_wifi off end + device ref sdxc off end + device ref i2c0 off end + device ref i2c1 off end + device ref i2c2 off end + device ref i2c3 off end + device ref heci1 on end + device ref heci2 off end + device ref csme_ider off end + device ref csme_ktr off end + device ref heci3 off end + device ref heci4 off end + device ref sata on register "SataSalpSupport" = "1" register "SataPortsEnable[0]" = "1" # HDD / SSD register "SataPortsEnable[1]" = "1" # ODD @@ -60,71 +60,71 @@ chip soc/intel/cannonlake register "SataPortsDevSlp[0]" = "1" # M.2 register "SataPortsDevSlp[2]" = "1" # HDD / SSD end - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on # PCI Express Port 5 + device ref i2c4 off end + device ref i2c5 off end + device ref uart2 off end + device ref emmc off end + device ref pcie_rp1 off end + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on device pci 00.0 on end # x1 i219 register "PcieRpEnable[4]" = "1" register "PcieClkSrcUsage[4]" = "0x70" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[4]" = "0" end - device pci 1c.5 on # PCI Express Port 6 + device ref pcie_rp6 on device pci 00.0 on end # x1 i210 register "PcieRpEnable[5]" = "1" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[5]" = "0" end - device pci 1c.6 on # PCI Express Port 7 + device ref pcie_rp7 on register "PcieRpEnable[6]" = "1" register "PcieRpSlotImplemented[6]" = "1" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X" end - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1b.0 on # PCI Express Port 17 + device ref pcie_rp8 off end + device ref pcie_rp9 off end + device ref pcie_rp10 off end + device ref pcie_rp11 off end + device ref pcie_rp12 off end + device ref pcie_rp13 off end + device ref pcie_rp14 off end + device ref pcie_rp15 off end + device ref pcie_rp16 off end + device ref pcie_rp17 on register "PcieRpEnable[16]" = "1" register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" end - device pci 1b.1 off end # PCI Express Port 18 - device pci 1b.2 off end # PCI Express Port 19 - device pci 1b.3 off end # PCI Express Port 20 - device pci 1b.4 off end # PCI Express Port 21 - device pci 1b.5 off end # PCI Express Port 22 - device pci 1b.6 off end # PCI Express Port 23 - device pci 1b.7 off end # PCI Express Port 24 - device pci 1e.0 off end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Interface + device ref pcie_rp18 off end + device ref pcie_rp19 off end + device ref pcie_rp20 off end + device ref pcie_rp21 off end + device ref pcie_rp22 off end + device ref pcie_rp23 off end + device ref pcie_rp24 off end + device ref uart0 off end + device ref uart1 off end + device ref gspi0 off end + device ref gspi1 off end + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.1 hidden end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 on end # GbE - device pci 1f.7 off end # TraceHub + device ref p2sb hidden end + device ref pmc hidden end + device ref hda on end + device ref smbus on end + device ref fast_spi on end + device ref gbe on end + device ref tracehub off end end end diff --git a/src/mainboard/siemens/chili/variants/chili/devicetree.cb b/src/mainboard/siemens/chili/variants/chili/devicetree.cb index cee1967a36..b514d74cf1 100644 --- a/src/mainboard/siemens/chili/variants/chili/devicetree.cb +++ b/src/mainboard/siemens/chili/variants/chili/devicetree.cb @@ -10,19 +10,19 @@ chip soc/intel/cannonlake device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 01.0 off end # PCIe x16 - device pci 01.1 off end # PCIe x8 - device pci 01.2 off end # PCIe x4 - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA Thermal device - device pci 05.0 off end # Imaging Processing Unit - device pci 08.0 off end # Gaussian mixture model, Neural network accelerator - device pci 12.0 on end # Thermal Subsystem - device pci 12.5 off end # UFS SCS - device pci 12.6 off end # GSPI #2 - device pci 13.0 off end # ISH - device pci 14.0 on # USB xHCI + device ref system_agent on end + device ref peg0 off end + device ref peg1 off end + device ref peg2 off end + device ref igpu on end + device ref dptf on end + device ref ipu off end + device ref gna off end + device ref thermal on end + device ref ufs off end + device ref gspi2 off end + device ref ish off end + device ref xhci on # USB2 register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Debug register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # ReinerSCT @@ -30,11 +30,11 @@ chip soc/intel/cannonlake # USB3 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # Debug end - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Shared SRAM - device pci 14.3 off end # CNVi Wifi - device pci 14.5 off end # SDCard - device pci 15.0 on # I2C #0 + device ref xdci off end + device ref shared_sram on end + device ref cnvi_wifi off end + device ref sdxc off end + device ref i2c0 on chip drivers/secunet/dmi device i2c 0x57 on end # Serial EEPROM end @@ -94,92 +94,92 @@ chip soc/intel/cannonlake }" end end - device pci 15.1 off end # I2C #1 - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 16.5 off end # Management Engine Interface 4 - device pci 17.0 off end # SATA - device pci 19.0 off end # I2C #4 - device pci 19.1 off end # I2C #5 - device pci 19.2 off end # UART #2 - device pci 1a.0 off end # eMMC - device pci 1c.0 off # PCI Express Port 1 + device ref i2c1 off end + device ref i2c2 off end + device ref i2c3 off end + device ref heci1 on end + device ref heci2 off end + device ref csme_ider off end + device ref csme_ktr off end + device ref heci3 off end + device ref heci4 off end + device ref sata off end + device ref i2c4 off end + device ref i2c5 off end + device ref uart2 off end + device ref emmc off end + device ref pcie_rp1 off register "PcieRpEnable[0]" = "0" # Debug (x1) register "PcieClkSrcUsage[2]" = "0" register "PcieClkSrcClkReq[2]" = "2" end - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on # PCI Express Port 5 + device ref pcie_rp2 off end + device ref pcie_rp3 off end + device ref pcie_rp4 off end + device ref pcie_rp5 on register "PcieRpEnable[4]" = "1" # CORE (x1) register "PcieClkSrcUsage[4]" = "4" register "PcieClkSrcClkReq[4]" = "4" register "PcieRpSlotImplemented[4]" = "1" end - device pci 1c.5 on # PCI Express Port 6 + device ref pcie_rp6 on device pci 00.0 on end # i210 (x1) register "PcieRpEnable[5]" = "1" register "PcieClkSrcUsage[5]" = "5" register "PcieClkSrcClkReq[5]" = "5" register "PcieRpSlotImplemented[5]" = "0" end - device pci 1c.6 on # PCI Express Port 7 - device pci 00.0 on end # VL805 Front Rack/UIB (x1) + device ref pcie_rp7 on + device pci 00.0 on end # VL805 Front Rack/UIB (x1) register "PcieRpEnable[6]" = "1" register "PcieClkSrcUsage[1]" = "6" register "PcieClkSrcClkReq[1]" = "1" register "PcieRpSlotImplemented[6]" = "0" end - device pci 1c.7 on # PCI Express Port 8 - device pci 00.0 on end # VL805 Back MB (x1) + device ref pcie_rp8 on + device pci 00.0 on end # VL805 Back MB (x1) register "PcieRpEnable[7]" = "1" register "PcieClkSrcUsage[0]" = "7" register "PcieClkSrcClkReq[0]" = "0" register "PcieRpSlotImplemented[7]" = "0" end - device pci 1d.0 off end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1d.4 off end # PCI Express Port 13 - device pci 1d.5 off end # PCI Express Port 14 - device pci 1d.6 off end # PCI Express Port 15 - device pci 1d.7 off end # PCI Express Port 16 - device pci 1b.0 on # PCI Express Port 17 + device ref pcie_rp9 off end + device ref pcie_rp10 off end + device ref pcie_rp11 off end + device ref pcie_rp12 off end + device ref pcie_rp13 off end + device ref pcie_rp14 off end + device ref pcie_rp15 off end + device ref pcie_rp16 off end + device ref pcie_rp17 on register "PcieRpEnable[16]" = "1" # NVMe (x4) register "PcieClkSrcUsage[7]" = "16" register "PcieClkSrcClkReq[7]" = "7" register "PcieRpSlotImplemented[16]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "2280" "SlotDataBusWidth4X" end - device pci 1b.1 off end # PCI Express Port 18 - device pci 1b.2 off end # PCI Express Port 19 - device pci 1b.3 off end # PCI Express Port 20 - device pci 1b.4 off end # PCI Express Port 21 - device pci 1b.5 off end # PCI Express Port 22 - device pci 1b.6 off end # PCI Express Port 23 - device pci 1b.7 off end # PCI Express Port 24 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1f.0 on # LPC Interface + device ref pcie_rp18 off end + device ref pcie_rp19 off end + device ref pcie_rp20 off end + device ref pcie_rp21 off end + device ref pcie_rp22 off end + device ref pcie_rp23 off end + device ref pcie_rp24 off end + device ref uart0 on end + device ref uart1 off end + device ref gspi0 off end + device ref gspi1 off end + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.1 hidden end # P2SB - device pci 1f.2 hidden end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - device pci 1f.7 off end # TraceHub + device ref p2sb hidden end + device ref pmc hidden end + device ref hda on end + device ref smbus on end + device ref fast_spi on end + device ref gbe off end + device ref tracehub off end end end