soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bits

Based on:

- Apollo Lake datasheet Vol. 3 Revision 005:
  https://cdrdv2.intel.com/v1/dl/getContent/334819
- 7th Generation Intel Processor Families I/O for U/Y Platforms
  Datasheet Vol.2 August 2017:
  https://cdrdv2.intel.com/v1/dl/getContent/334659
- edk2-platforms source for Whitley and Purley platforms (Xeon SP)

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>

src/soc/intel/apollolake/include/soc/pm.h

@@ -172,7 +172,12 @@
 #define  BIOS_PCI_EXP_EN	(1 << 10)
 #define  PWRBTN_LVL		(1 <<  9)
 #define  SMI_LOCK		(1 <<  4)
-#define  PER_SMI_SEL		(1 <<  0)
+#define  PER_SMI_SEL_MASK	(3 <<  0)
+#define    SMI_RATE_64S		(0 <<  0)
+#define    SMI_RATE_32S		(1 <<  0)
+#define    SMI_RATE_16S		(2 <<  0)
+#define    SMI_RATE_8S		(3 <<  0)
+
 #define GEN_PMCON3		0x1028
 #define  SLP_S3_ASSERT_WIDTH_SHIFT	10
 #define  SLP_S3_ASSERT_MASK	(0x3 << SLP_S3_ASSERT_WIDTH_SHIFT)

src/soc/intel/skylake/include/soc/pmc.h

@@ -35,6 +35,12 @@
 #define  ALLOW_L1LOW_C0		(1 << 7)
 #define  ALLOW_L1LOW_OPI_ON	(1 << 6)
 #define  SMI_LOCK		(1 << 4)
+#define  PER_SMI_SEL_MASK	(3 << 0)
+#define    SMI_RATE_64S		(0 << 0)
+#define    SMI_RATE_32S		(1 << 0)
+#define    SMI_RATE_16S		(2 << 0)
+#define    SMI_RATE_8S		(3 << 0)
+
 #define GEN_PMCON_B		0xa4
 #define  SLP_STR_POL_LOCK	(1 << 18)
 #define  ACPI_BASE_LOCK		(1 << 17)

src/soc/intel/xeon_sp/lbg/include/soc/pmc.h

@@ -25,6 +25,11 @@
 #define  MS4V			(1 << 18)
 #define  GBL_RST_STS		(1 << 16)
 #define  SMI_LOCK		(1 << 4)
+#define  PER_SMI_SEL_MASK	(3 << 1)
+#define    SMI_RATE_64S		(0 << 1)
+#define    SMI_RATE_32S		(1 << 1)
+#define    SMI_RATE_16S		(2 << 1)
+#define    SMI_RATE_8S		(3 << 1)
 #define GEN_PMCON_B		0xa4
 #define  SLP_STR_POL_LOCK	(1 << 18)
 #define  ACPI_BASE_LOCK		(1 << 17)