sb/amd/cimx/sb800: Postpone Sb_Poweron_Init() call
With LPC decode enables explicitly set in C env bootblock, this call can be delayed to happen before AMD_INIT_RESET. Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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24f0455016
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3d5e1e5d52
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@ -12,7 +12,6 @@
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#
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romstage-y += fixme.c
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romstage-y += romstage.c
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ramstage-y += fixme.c
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ramstage-y += chip_name.c
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@ -1,24 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <northbridge/amd/agesa/state_machine.h>
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#include <sb_cimx.h>
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void platform_once(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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board_BeforeAgesa(cb);
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}
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@ -29,11 +29,6 @@
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void __weak board_BeforeAgesa(struct sysinfo *cb) { }
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void __weak platform_once(struct sysinfo *cb)
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{
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board_BeforeAgesa(cb);
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}
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static void fill_sysinfo(struct sysinfo *cb)
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{
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memset(cb, 0, sizeof(*cb));
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@ -67,7 +62,7 @@ static void romstage_main(void)
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timestamp_init(timestamp_get());
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timestamp_add_now(TS_START_ROMSTAGE);
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platform_once(cb);
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board_BeforeAgesa(cb);
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console_init();
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}
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@ -15,11 +15,13 @@
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#include <northbridge/amd/agesa/state_machine.h>
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#include <superio/smsc/kbc1100/kbc1100.h>
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#include <sb_cimx.h>
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#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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kbc1100_early_init(0x2e);
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kbc1100_early_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -16,10 +16,12 @@
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#include <northbridge/amd/agesa/state_machine.h>
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#include <superio/fintek/common/fintek.h>
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#include <superio/fintek/f81865f/f81865f.h>
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#include <sb_cimx.h>
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#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -16,10 +16,12 @@
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#include <northbridge/amd/agesa/state_machine.h>
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#include <superio/fintek/common/fintek.h>
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#include <superio/fintek/f81865f/f81865f.h>
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#include <sb_cimx.h>
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#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -14,7 +14,9 @@
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*/
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#include <northbridge/amd/agesa/state_machine.h>
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#include <sb_cimx.h>
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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}
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@ -16,11 +16,13 @@
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#include <northbridge/amd/agesa/state_machine.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct5572d/nct5572d.h>
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#include <sb_cimx.h>
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#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -16,10 +16,12 @@
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#include <northbridge/amd/agesa/state_machine.h>
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#include <superio/fintek/common/fintek.h>
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#include <superio/fintek/f81865f/f81865f.h>
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#include <sb_cimx.h>
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#define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -15,7 +15,9 @@
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*/
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#include <northbridge/amd/agesa/state_machine.h>
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#include <sb_cimx.h>
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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}
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@ -17,11 +17,13 @@
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#include <northbridge/amd/agesa/state_machine.h>
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#include <superio/fintek/common/fintek.h>
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#include <superio/fintek/f71869ad/f71869ad.h>
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#include <sb_cimx.h>
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/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */
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#define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -15,10 +15,12 @@
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#include <northbridge/amd/agesa/state_machine.h>
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#include <superio/smsc/smscsuperio/smscsuperio.h>
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#include <sb_cimx.h>
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#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -16,10 +16,12 @@
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#include <northbridge/amd/agesa/state_machine.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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#include <sb_cimx.h>
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#define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -21,6 +21,7 @@
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#include <superio/nuvoton/nct5104d/nct5104d.h>
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#include "gpio_ftns.h"
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#include <SB800.h>
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#include <sb_cimx.h>
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#define SIO_PORT 0x2e
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#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
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void board_BeforeAgesa(struct sysinfo *cb)
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{
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sb_Poweron_Init();
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early_lpc_init();
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nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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@ -29,24 +29,30 @@
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void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset)
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{
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if (!boot_cpu())
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return;
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if (!CONFIG(ROMCC_BOOTBLOCK))
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sb_Poweron_Init();
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/* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all
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* would fail later in AmdInitPost(), when DRAM is already configured
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* and C6DramLock bit has been set.
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*
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* As a workaround, do a hard reset to clear C6DramLock bit.
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*/
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#ifdef __SIMPLE_DEVICE__
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pci_devfn_t dev = PCI_DEV(0, 0x18, 2);
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#else
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struct device *dev = pcidev_on_root(0x18, 2);
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#endif
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if (boot_cpu()) {
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u32 mct_cfg_lo = pci_read_config32(dev, 0x118);
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if (mct_cfg_lo & (1<<19)) {
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printk(BIOS_CRIT, "C6DramLock is set, resetting\n");
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system_reset();
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}
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u32 mct_cfg_lo = pci_read_config32(dev, 0x118);
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if (mct_cfg_lo & (1<<19)) {
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printk(BIOS_CRIT, "C6DramLock is set, resetting\n");
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system_reset();
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}
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}
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void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
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};
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void board_BeforeAgesa(struct sysinfo *cb);
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void platform_once(struct sysinfo *cb);
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void agesa_set_interface(struct sysinfo *cb);
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