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mediatek/mt8173: Add a stub implementation of the MT8173 SoC 

BUG=chrome-os-partner:36682
TEST=emerge-oak coreboot
BRANCH=none

Change-Id: I748752d5abca813a0469d3a76e4d40fcbeb9b959
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ece2f412d94f071a6f5f1dbed4dfaea504da9e1a
Original-Change-Id: I1dd5567a10d20840313703cfcd328bec591b4941
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292558
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12587
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Yidi Lin 2015-07-31 17:10:40 +08:00 committed by Patrick Georgi
parent f82e8ab697
commit 3d7b6069e1
24 changed files with 1350 additions and 0 deletions
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49
src/mainboard/google/oak/Kconfig Normal file
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##
## This file is part of the coreboot project.
##
## Copyright 2015 MediaTek Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
if BOARD_GOOGLE_OAK
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_MEDIATEK_MT8173
select CHROMEOS_VBNV_EC
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_SPI
select EC_SOFTWARE_SYNC
select MAINBOARD_HAS_NATIVE_VGA_INIT
select MAINBOARD_DO_NATIVE_VGA_INIT
select VIRTUAL_DEV_SWITCH
config MAINBOARD_DIR
string
default google/oak
config MAINBOARD_PART_NUMBER
string
default "oak"
config DRAM_SIZE_MB
int
default 2048
config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 0
endif # BOARD_GOOGLE_OAK

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src/mainboard/google/oak/Kconfig.name Normal file
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config BOARD_GOOGLE_OAK
bool "Oak"

31
src/mainboard/google/oak/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright 2015 MediaTek Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
bootblock-y += bootblock.c
bootblock-y += memlayout.ld
bootblock-y += chromeos.c
romstage-y += chromeos.c
romstage-y += romstage.c
romstage-y += memlayout.ld
ramstage-y += mainboard.c
ramstage-y += chromeos.c
ramstage-y += memlayout.ld

33
src/mainboard/google/oak/bootblock.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <bootblock_common.h>
#include <delay.h>
#include <soc/pericfg.h>
void bootblock_mainboard_early_init(void)
{
/* Clear UART0 power down signal */
clrbits_le32(&mt8173_pericfg->pdn0_set, PERICFG_UART0_PDN);
}
void bootblock_mainboard_init(void)
{
}

40
src/mainboard/google/oak/chromeos.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <boot/coreboot_tables.h>
#include <vendorcode/google/chromeos/chromeos.h>
void fill_lb_gpios(struct lb_gpios *gpios)
{
}
int get_developer_mode_switch(void)
{
return 0;
}
int get_recovery_mode_switch(void)
{
return 0;
}
int get_write_protect_state(void)
{
return 0;
}

24
src/mainboard/google/oak/devicetree.cb Normal file
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##
## This file is part of the coreboot project.
##
## Copyright 2015 MediaTek Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
chip soc/mediatek/mt8173
device cpu_cluster 0 on
device cpu 0 on end
end
end

38
src/mainboard/google/oak/mainboard.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/cache.h>
#include <arch/io.h>
#include <boardid.h>
#include <boot/coreboot_tables.h>
#include <device/device.h>
static void mainboard_init(device_t dev)
{
}
static void mainboard_enable(device_t dev)
{
dev->ops->init = &mainboard_init;
}
struct chip_operations mainboard_ops = {
.name = "oak",
.enable_dev = mainboard_enable,
};

1
src/mainboard/google/oak/memlayout.ld Normal file
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#include <soc/memlayout.ld>

38
src/mainboard/google/oak/romstage.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/cache.h>
#include <arch/cpu.h>
#include <arch/exception.h>
#include <arch/io.h>
#include <cbfs.h>
#include <console/console.h>
#include <delay.h>
#include <program_loading.h>
#include <romstage_handoff.h>
#include <symbols.h>
void main(void)
{
/* init uart baudrate when pll on */
console_init();
exception_init();
run_ramstage();
}

49
src/soc/mediatek/mt8173/Kconfig Normal file
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config SOC_MEDIATEK_MT8173
bool
default n
select ARM64_A53_ERRATUM_843419
select ARCH_BOOTBLOCK_ARMV8_64
select ARCH_RAMSTAGE_ARMV8_64
select ARCH_ROMSTAGE_ARMV8_64
select ARCH_VERSTAGE_ARMV8_64
select BOOTBLOCK_CONSOLE
select HAVE_UART_SPECIAL
select SPI_ATOMIC_SEQUENCING
select HAVE_MONOTONIC_TIMER
select GENERIC_UDELAY
select HAS_PRECBMEM_TIMESTAMP_REGION
if SOC_MEDIATEK_MT8173
config DEBUG_SOC_DRIVER
bool "The top level switch for soc driver debug message"
default n
select DEBUG_DRAM
select DEBUG_I2C
select DEBUG_PMIC
select DEBUG_PMIC_WRAP
config DEBUG_DRAM
bool "Output verbose DRAM related debug message"
default n
help
This option enables additional DRAM related debug messages.
config DEBUG_I2C
bool "Output verbose I2C related debug message"
default n
help
This option enables I2C related debug message.
config DEBUG_PMIC
bool "Output verbose PMIC related debug message"
default n
help
This option enables PMIC related debug message.
config DEBUG_PMIC_WRAP
bool "Output verbose PMIC WRAP related debug message"
default n
help
This option enables PMIC WRAP related debug message.
endif

50
src/soc/mediatek/mt8173/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright 2015 MediaTek Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
ifeq ($(CONFIG_SOC_MEDIATEK_MT8173),y)
bootblock-y += bootblock.c
bootblock-y += cbfs.c
bootblock-y += timer.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += uart.c
endif
################################################################################
romstage-y += cbfs.c
romstage-y += timer.c
romstage-$(CONFIG_DRIVERS_UART) += uart.c
romstage-y += cbmem.c
################################################################################
ramstage-y += cbmem.c
ramstage-y += cbfs.c
ramstage-y += soc.c
ramstage-y += timer.c
ramstage-$(CONFIG_DRIVERS_UART) += uart.c
################################################################################
CPPFLAGS_common += -Isrc/soc/mediatek/mt8173/include
endif

24
src/soc/mediatek/mt8173/bootblock.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <bootblock_common.h>
void bootblock_soc_init(void)
{
}

25
src/soc/mediatek/mt8173/cbfs.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <boot_device.h>
const struct region_device *boot_device_ro(void)
{
return NULL;
}

27
src/soc/mediatek/mt8173/cbmem.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cbmem.h>
#include <stddef.h>
#include <symbols.h>
void *cbmem_top(void)
{
return (void *)((uintptr_t) _dram + (CONFIG_DRAM_SIZE_MB << 20));
}

62
src/soc/mediatek/mt8173/include/soc/addressmap.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__
#define __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H__
#include <stddef.h>
#include <stdint.h>
enum {
VER_BASE = 0x08000000,
IO_PHYS = 0x10000000,
DDR_BASE = 0x40000000
};
enum {
CKSYS_BASE = IO_PHYS,
INFRACFG_AO_BASE = IO_PHYS + 0x1000,
PERI_CON_BASE = IO_PHYS + 0x3000,
CHA_DRAMCAO_BASE = IO_PHYS + 0x4000,
GPIO_BASE = IO_PHYS + 0x5000,
SPM_BASE = IO_PHYS + 0x6000,
RGU_BASE = IO_PHYS + 0x7000,
GPT_BASE = IO_PHYS + 0x8000,
PMIC_WRAP_BASE = IO_PHYS + 0xD000,
CHA_DDRPHY_BASE = IO_PHYS + 0xF000,
CHB_DRAMCAO_BASE = IO_PHYS + 0x11000,
CHB_DDRPHY_BASE = IO_PHYS + 0x12000,
MCUCFG_BASE = IO_PHYS + 0x200000,
EMI_BASE = IO_PHYS + 0x203000,
EFUSE_BASE = IO_PHYS + 0x206000,
APMIXED_BASE = IO_PHYS + 0x209000,
CHA_DRAMCNAO_BASE = IO_PHYS + 0x20E000,
CHB_DRAMCNAO_BASE = IO_PHYS + 0x213000,
ANA_MIPI_CS1_BASE = IO_PHYS + 0x218000,
UART0_BASE = IO_PHYS + 0x1002000,
SPI_BASE = IO_PHYS + 0x100A000,
I2C_BASE = IO_PHYS + 0x1007000,
I2C_DMA_BASE = IO_PHYS + 0x1000080,
SFLASH_REG_BASE = IO_PHYS + 0x100D000,
SSUSB_MAC_BASE = IO_PHYS + 0x1270000,
SSUSB_IPPC_BASE = IO_PHYS + 0x1280700,
SSUSB_SIF_BASE = IO_PHYS + 0x1290800,
};
#endif /* __SOC_MEDIATEK_MT8173_INCLUDE_SOC_ADDRESS_MAP_H___ */

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src/soc/mediatek/mt8173/include/soc/infracfg.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __SOC_MEDIATEK_MT8173_INFRACFG_H__
#define __SOC_MEDIATEK_MT8173_INFRACFG_H__
#include <soc/addressmap.h>
#include <types.h>
struct mt8173_infracfg_regs {
u32 top_ckmuxsel;
u32 reserved0;
u32 top_ckdiv1;
u32 reserved1;
u32 top_dcmctl;
u32 top_dcmdbc;
u32 reserved2[6];
u32 infra_rst0;
u32 infra_rst1;
u32 reserved3[2];
u32 infra_pdn0;
u32 infra_pdn1;
u32 reserved4[118];
u32 topaxi_prot_en;
u32 topaxi_prot_sta0;
u32 topaxi_prot_sta1; /* 0x228 */
};
check_member(mt8173_infracfg_regs, infra_pdn0, 0x40);
check_member(mt8173_infracfg_regs, topaxi_prot_sta1, 0x228);
static struct mt8173_infracfg_regs *const mt8173_infracfg =
(void *)INFRACFG_AO_BASE;
enum {
INFRA_PMIC_WRAP_RST = 1 << 7,
L2C_SRAM_PDN = 1 << 7
};
#endif /* __SOC_MEDIATEK_MT8173_INFRACFG_H__ */

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src/soc/mediatek/mt8173/include/soc/mcucfg.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __SOC_MEDIATEK_MT8173_MCUCFG_H__
#define __SOC_MEDIATEK_MT8173_MCUCFG_H__
#include <soc/addressmap.h>
struct mt8173_mcucfg_regs {
u32 mp0_ca7l_cache_config;
struct {
u32 mem_delsel0;
u32 mem_delsel1;
} mp0_cpu[4];
u32 mp0_cache_mem_delsel0;
u32 mp0_cache_mem_delsel1;
u32 mp0_axi_config;
u32 mp0_misc_config[10];
u32 mp0_ca7l_cfg_dis;
u32 mp0_ca7l_clken_ctrl;
u32 mp0_ca7l_rst_ctrl;
u32 mp0_ca7l_misc_config;
u32 mp0_ca7l_dbg_pwr_ctrl;
u32 mp0_rw_rsvd0;
u32 mp0_rw_rsvd1;
u32 mp0_ro_rsvd;
u32 reserved0_0[100];
u32 mp1_cpucfg;
u32 mp1_miscdbg;
u32 reserved0_1[13];
u32 mp1_rst_ctl;
u32 mp1_clkenm_div;
u32 reserved0_2[7];
u32 mp1_config_res;
u32 reserved0_3[101];
u32 mp0_rst_status; /* 0x400 */
u32 mp0_dbg_ctrl;
u32 mp0_dbg_flag;
u32 mp0_ca7l_ir_mon;
struct {
u32 pc_lw;
u32 pc_hw;
u32 fp_arch32;
u32 sp_arch32;
u32 fp_arch64_lw;
u32 fp_arch64_hw;
u32 sp_arch64_lw;
u32 sp_arch64_hw;
} mp0_dbg_core[4];
u32 dfd_ctrl;
u32 dfd_cnt_l;
u32 dfd_cnt_h;
u32 misccfg_mp0_rw_rsvd;
u32 misccfg_sec_vio_status0;
u32 misccfg_sec_vio_status1;
u32 reserved1[22];
u32 misccfg_rw_rsvd; /* 0x500 */
u32 mcusys_dbg_mon_sel_a;
u32 mcusys_dbg_mon;
u32 reserved2[61];
u32 mcusys_config_a; /* 0x600 */
u32 mcusys_config1_a;
u32 mcusys_gic_peribase_a;
u32 reserved3;
u32 sec_range0_start; /* 0x610 */
u32 sec_range0_end;
u32 sec_range_enable;
u32 reserved4;
u32 int_pol_ctl[8]; /* 0x620 */
u32 aclken_div; /* 0x640 */
u32 pclken_div;
u32 l2c_sram_ctrl;
u32 armpll_jit_ctrl;
u32 cci_addrmap; /* 0x650 */
u32 cci_config;
u32 cci_periphbase;
u32 cci_nevntcntovfl;
u32 cci_clk_ctrl; /* 0x660 */
u32 cci_acel_s1_ctrl;
u32 bus_fabric_dcm_ctrl;
u32 reserved5;
u32 xgpt_ctl; /* 0x670 */
u32 xgpt_idx;
u32 ptpod2_ctl0;
u32 ptpod2_ctl1;
u32 mcusys_revid;
u32 mcusys_rw_rsvd0;
u32 mcusys_rw_rsvd1;
};
check_member(mt8173_mcucfg_regs, mcusys_rw_rsvd1, 0x688);
static struct mt8173_mcucfg_regs * const mt8173_mcucfg = (void *)MCUCFG_BASE;
#endif /* __SOC_MEDIATEK_MT8173_MCUCFG_H__ */

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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <memlayout.h>
#include <arch/header.ld>
/*
* SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM.
* It will be returned before starting the ramstage.
* SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
*/
#define SRAM_L2C_START(addr) SYMBOL(sram_l2c, addr)
#define SRAM_L2C_END(addr) SYMBOL(esram_l2c, addr)
SECTIONS
{
SRAM_L2C_START(0x000C0000)
BOOTBLOCK(0x000C1000, 85K)
VERSTAGE(0x000D7000, 114K)
PRERAM_CBFS_CACHE(0x000F6000, 16K)
SRAM_L2C_END(0x00100000)
SRAM_START(0x00100000)
VBOOT2_WORK(0x00100000, 12K)
PRERAM_CBMEM_CONSOLE(0x00103000, 16K)
TIMESTAMP(0x00107000, 4K)
ROMSTAGE(0x00108000, 92K)
STACK(0x00124000, 16K)
TTB(0x00128000, 28K)
DMA_COHERENT(0x0012F000, 4K)
SRAM_END(0x00130000)
DRAM_START(0x40000000)
POSTRAM_CBFS_CACHE(0x40100000, 1M)
RAMSTAGE(0x40200000, 256K)
}

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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __SOC_MEDIATEK_MT8173_PERICFG_H__
#define __SOC_MEDIATEK_MT8173_PERICFG_H__
#include <soc/addressmap.h>
#include <types.h>
struct mt8173_pericfg_regs {
u32 rst0;
u32 rst1;
u32 pdn0_set;
u32 pdn1_set;
u32 pdn0_clr;
u32 pdn1_clr;
u32 pdn0_sta;
u32 pdn1_sta;
u32 pdn_md1_set;
u32 pdn_md2_set;
u32 pdn_md1_clr;
u32 pdn_md2_clr;
u32 pdn_md1_sta;
u32 pdn_md2_sta;
u32 pdn_md_mask;
u32 reserved0[5];
u32 dcmctl;
u32 dcmdbc;
u32 dcmfsel;
u32 cksel;
u32 reserved1[104];
u32 axi_bus_ctl1;
u32 axi_bus_ctl2;
u32 axi_bus_ctl3;
u32 axi_si0_ctl;
u32 axi_si1_ctl;
u32 axi_mi_sta;
u32 reserved2[58];
u32 axi_ahb_lmt_con1;
u32 axi_ahb_lmt_con2;
u32 axi_ahb_lmt_con3;
u32 axi_ahb_lmt_con4;
u32 axi_ahb_lmt_con5;
u32 axi_ahb_lmt_con6;
u32 reserved3[2];
u32 axi_axi_lmt_con1;
u32 axi_axi_lmt_con2;
u32 axi_axi_lmt_con3;
u32 axi_axi_lmt_con4;
u32 axi_axi_lmt_con5;
u32 axi_axi_lmt_con6;
u32 axi_axi_lmt_con7;
u32 axi_axi_lmt_con8;
u32 axi_axi_lmt_con9;
u32 reserved4[47];
u32 usb_wakeup_dec_con0;
u32 usb_wakeup_dec_con1;
u32 usb_wakeup_dec_con2;
u32 uart_ck_source_sel;
u32 reserved5[1];
u32 usb_wakeup_dec_con3a;
u32 reserved6[58];
u32 ssusb_rst;
u32 ssusb_pdn_set;
u32 ssusb_pdn_clr;
u32 ssusb_pdn_sta;
};
static struct mt8173_pericfg_regs * const mt8173_pericfg =
(void *)PERI_CON_BASE;
/*
* UART power down control
*/
enum {
PERICFG_UART0_PDN = 1 << 19
};
#endif /* __SOC_MEDIATEK_MT8173_PERICFG_H__ */

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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __SOC_MEDIATEK_MT8173_SPM_H__
#define __SOC_MEDIATEK_MT8173_SPM_H__
#include <soc/addressmap.h>
#include <stddef.h>
enum {
SPM_PROJECT_CODE = 0xb16
};
struct mt8173_spm_regs {
u32 poweron_config_set;
u32 reserved1[3];
u32 power_on_val0; /* 0x010 */
u32 power_on_val1;
u32 reserved2[58];
u32 clk_settle; /* 0x100 */
u32 reserved3[63];
u32 ca7_cpu0_pwr_con; /* 0x200 */
u32 ca7_dbg_pwr_con;
u32 ca7_cputop_pwr_con;
u32 reserved4;
u32 vde_pwr_con; /* 0x210 */
u32 mfg_pwr_con;
u32 ca7_cpu1_pwr_con; /* 0x218 */
u32 ca7_cpu2_pwr_con;
u32 ca7_cpu3_pwr_con; /* 0x220 */
u32 reserved5[3];
u32 ven_pwr_con; /* 0x230 */
u32 ifr_pwr_con;
u32 isp_pwr_con;
u32 dis_pwr_con;
u32 dpy_pwr_con; /* 0x240 */
u32 ca7_cputop_l2_pdn; /* 0x244 */
u32 ca7_cputop_l2_sleep;
u32 reserved6[4];
struct { /* 0x25c */
u32 l1_pdn;
u32 reserved;
} ca7_cpu[4];
u32 gcpu_sram_con; /* 0x27c */
u32 dpy2_pwr_con; /* 0x280 */
u32 md_pwr_con;
u32 reserved11[2];
u32 mcu_pwr_con; /* 0x290 */
u32 ifr_sramrom_con;
u32 mjc_pwr_con;
u32 audio_pwr_con;
u32 ca15_cpu_pwr_con[4]; /* 0x2a0 */
u32 ca15_cputop_pwr_con; /* 0x2b0 */
u32 ca15_l1_pwr_con; /* 0x2b4 */
u32 ca15_l2_pwr_con; /* 0x2b8 */
u32 reserved12;
u32 mfg_2d_pwr_con; /* 0x2c0 */
u32 mfg_async_pwr_con;
u32 vpu_sram_con;
u32 reserved13[17];
u32 pcm_con0; /* 0x310 */
u32 pcm_con1;
u32 pcm_im_ptr;
u32 pcm_im_len;
u32 pcm_reg_data_ini; /* 0x320 */
u32 reserved14[7];
u32 pcm_event_vector0; /* 0x340 */
u32 pcm_event_vector1;
u32 pcm_event_vector2;
u32 pcm_event_vector3;
u32 reserved15;
u32 pcm_mas_pause_mask; /* 0x354 */
u32 pcm_pwr_io_en;
u32 pcm_timer_val;
u32 pcm_timer_out;
u32 reserved16[7];
u32 pcm_reg_data[16]; /* 0x380 */
u32 pcm_event_reg_sta;
u32 pcm_fsm_sta;
u32 pcm_im_host_rw_ptr;
u32 pcm_im_host_rw_dat;
u32 pcm_event_vector4;
u32 pcm_event_vector5;
u32 pcm_event_vector6;
u32 pcm_event_vector7;
u32 pcm_sw_int_set;
u32 pcm_sw_int_clear;
u32 reserved17[6];
u32 clk_con; /* 0x400 */
u32 sleep_dual_vcore_pwr_con; /* 0x404 */
u32 sleep_ptpod2_con;
u32 reserved18[125];
u32 apmcu_pwrctl; /* 0x600 */
u32 ap_dvfs_con_set;
u32 ap_stanby_con;
u32 pwr_status; /* 0x60c */
u32 pwr_status_2nd; /* 0x610 */
u32 ap_bsi_req;
u8 reserved19[0x720 - 0x618];
u32 sleep_timer_sta; /* 0x720 */
u32 reserved20[15];
u32 sleep_twam_con; /* 0x760 */
u32 sleep_twam_status0;
u32 sleep_twam_status1;
u32 sleep_twam_status2;
u32 sleep_twam_status3; /* 0x770 */
u32 reserved21[39];
u32 sleep_wakeup_event_mask; /* 0x810 */
u32 sleep_cpu_wakeup_event;
u32 sleep_md32_wakeup_event_mask;
u32 reserved22[2];
u32 pcm_wdt_timer_val; /* 0x824 */
u32 pcm_wdt_timer_out;
u32 reserved23;
u32 pcm_md32_mailbox; /* 0x830 */
u32 pcm_md32_irq;
u32 reserved24[50];
u32 sleep_isr_mask; /* 0x900 */
u32 sleep_isr_status;
u32 reserved25[2];
u32 sleep_isr_raw_sta; /* 0x910 */
u32 sleep_md32_isr_raw_sta;
u32 sleep_wakeup_misc;
u32 sleep_bus_protect_rdy;
u32 sleep_subsys_idle_sta; /* 0x920 */
u8 reserved26[0xb00 - 0x924];
u32 pcm_reserve; /* 0xb00 */
u32 pcm_reserve2;
u32 pcm_flags;
u32 pcm_src_req;
u32 reserved27[4];
u32 pcm_debug_con; /* 0xb20 */
u32 reserved28[3];
u32 ca7_cpu_irq_mask[4]; /* 0xb30 */
u32 ca15_cpu_irq_mask[4];
u32 reserved29[4];
u32 pcm_pasr_dpd[4]; /* 0xb60 */
u8 reserved30[0xf00 - 0xb70];
u32 sleep_ca7_wfi_en[4]; /* 0xf00 */
u32 sleep_ca15_wfi_en[4];
};
check_member(mt8173_spm_regs, sleep_ca15_wfi_en[3], 0xf1c);
static struct mt8173_spm_regs * const mt8173_spm = (void *)SPM_BASE;
#endif /* __SOC_MEDIATEK_MT8173_SPM_H__ */

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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef __SOC_MEDIATEK_MT8173_TIMER_H__
#define __SOC_MEDIATEK_MT8173_TIMER_H__
#include <soc/addressmap.h>
#include <types.h>
struct mt8173_gpt_regs {
u32 irqen;
u32 irqsta;
u32 irqack;
u32 reserved0;
u32 gpt1_con;
u32 gpt1_clk;
u32 gpt1_cnt;
u32 gpt1_compare;
u32 gpt2_con;
u32 gpt2_clk;
u32 gpt2_cnt;
u32 gpt2_compare;
u32 gpt3_con;
u32 gpt3_clk;
u32 gpt3_cnt;
u32 gpt3_compare;
u32 gpt4_con;
u32 gpt4_clk;
u32 gpt4_cnt;
u32 gpt4_compare;
u32 gpt5_con;
u32 gpt5_clk;
u32 gpt5_cnt;
u32 gpt5_compare;
u32 gpt6_con;
u32 gpt6_clk;
u32 gpt6_cntl;
u32 gpt6_comparel;
u32 reserved1[2];
u32 gpt6_cnth;
u32 gpt6_compareh;
u32 apxgpt_irqmask;
u32 apxgpt_irqmask1;
};
static struct mt8173_gpt_regs * const mt8173_gpt = (void *)GPT_BASE;
enum {
GPT_CON_EN = 0x01,
GPT_CON_CLR = 0x02,
GPT_MODE_ONE_SHOT = 0x00,
GPT_MODE_REPEAT = 0x10,
GPT_MODE_KEEP_GO = 0x20,
GPT_MODE_FREERUN = 0x30,
GPT_SYS_CLK = 0x00,
GPT_SYS_RTC = 0x01,
};
#endif /* __SOC_MEDIATEK_MT8173_TIMER_H__ */

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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/cpu.h>
#include <console/console.h>
#include <device/device.h>
#include <symbols.h>
static void soc_read_resources(device_t dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB,
CONFIG_DRAM_SIZE_MB * KiB);
}
static void soc_init(device_t dev)
{
}
static struct device_operations soc_ops = {
.read_resources = soc_read_resources,
.init = soc_init,
};
static void enable_soc_dev(device_t dev)
{
dev->ops = &soc_ops;
}
struct chip_operations soc_mediatek_mt8173_ops = {
CHIP_NAME("SOC Mediatek MT8173\n")
.enable_dev = enable_soc_dev,
};

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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <console/console.h>
#include <timer.h>
#include <delay.h>
#include <thread.h>
#include <soc/addressmap.h>
#include <soc/mcucfg.h>
#include <soc/timer.h>
#define GPT4_MHZ 13
void timer_monotonic_get(struct mono_time *mt)
{
mono_time_set_usecs(mt, read32(&mt8173_gpt->gpt4_cnt) / GPT4_MHZ);
}
/**
* init_timer - initialize timer
*/
void init_timer(void)
{
/* Set XGPT_IDX to 0, then the bit field of XGPT_CTL will be programmed
* with following definition.
*
* [10: 8] Clock mode
* 100: 26Mhz / 4
* 010: 26Mhz / 2
* 001: 26Mhz
* [ 1: 1] Halt-on-debug enable bit
* [ 0: 0] XGPT enable bit
*/
write32(&mt8173_mcucfg->xgpt_idx, 0);
/* Set clock mode to 13Mhz and enable XGPT */
write32(&mt8173_mcucfg->xgpt_ctl, (0x1 | ((26 / GPT4_MHZ) << 8)));
/* Disable GPT4 and clear the counter */
clrbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_EN);
setbits_le32(&mt8173_gpt->gpt4_con, GPT_CON_CLR);
/* Set clock source to system clock and set clock divider to 1 */
write32(&mt8173_gpt->gpt4_clk, GPT_SYS_CLK | 0x0);
/* Set operation mode to FREERUN mode and enable GTP4 */
write32(&mt8173_gpt->gpt4_con, GPT_CON_EN | GPT_MODE_FREERUN);
}

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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <boot/coreboot_tables.h>
#include <console/console.h> /* for __console definition */
#include <console/uart.h>
#include <drivers/uart/uart8250reg.h>
#include <stdint.h>
#include <soc/addressmap.h>
struct mtk_uart {
union {
uint32_t thr; /* Transmit holding register. */
uint32_t rbr; /* Receive buffer register. */
uint32_t dll; /* Divisor latch lsb. */
};
union {
uint32_t ier; /* Interrupt enable register. */
uint32_t dlm; /* Divisor latch msb. */
};
union {
uint32_t iir; /* Interrupt identification register. */
uint32_t fcr; /* FIFO control register. */
uint32_t efr; /* Enhanced feature register. */
};
uint32_t lcr; /* Line control register. */
union {
uint32_t mcr; /* Modem control register. */
uint32_t xn1; /* XON1 */
};
union {
uint32_t lsr; /* Line status register. */
uint32_t xn2; /* XON2 */
};
union {
uint32_t msr; /* Modem status register. */
uint32_t xf1; /* XOFF1 */
};
union {
uint32_t scr; /* Scratch register. */
uint32_t xf2; /* XOFF2 */
};
uint32_t autobaud_en; /* Enable auto baudrate. */
uint32_t highspeed; /* High speed UART. */
} __attribute__ ((packed));
/* Peripheral Reset and Power Down registers */
struct mtk_peri_globalcon {
uint32_t rst0;
uint32_t rst1;
uint32_t pdn0_set;
uint32_t pdn1_set;
uint32_t pdn0_clr;
uint32_t pdn1_clr;
uint32_t pdn0_sta;
uint32_t pdn1_sta;
uint32_t pdn_md1_set;
uint32_t pdn_md2_set;
uint32_t pdn_md1_clr;
uint32_t pdn_md2_clr;
uint32_t pdn_md1_sta;
uint32_t pdn_md2_sta;
uint32_t pdn_md_mask;
} __attribute__ ((packed));
static struct mtk_uart *const uart_ptr = (void *)UART0_BASE;
static void mtk_uart_tx_flush(void);
static int mtk_uart_tst_byte(void);
static void mtk_uart_init(void)
{
/* Use a hardcoded divisor for now. */
const unsigned uartclk = 26 * MHz;
const unsigned baudrate = CONFIG_TTYS0_BAUD;
const uint8_t line_config = UART8250_LCR_WLS_8; /* 8n1 */
unsigned highspeed, quot, divisor, remainder;
if (baudrate <= 115200) {
highspeed = 0;
quot = 16;
} else {
highspeed = 2;
quot = 4;
}
/* Set divisor DLL and DLH */
divisor = uartclk / (quot * baudrate);
remainder = uartclk % (quot * baudrate);
if (remainder >= (quot / 2) * baudrate)
divisor += 1;
mtk_uart_tx_flush();
/* Disable interrupts. */
write8(&uart_ptr->ier, 0);
/* Force DTR and RTS to high. */
write8(&uart_ptr->mcr, UART8250_MCR_DTR | UART8250_MCR_RTS);
/* Set High speed UART register. */
write8(&uart_ptr->highspeed, highspeed);
/* Set line configuration, access divisor latches. */
write8(&uart_ptr->lcr, UART8250_LCR_DLAB | line_config);
/* Set the divisor. */
write8(&uart_ptr->dll, divisor & 0xff);
write8(&uart_ptr->dlm, (divisor >> 8) & 0xff);
/* Hide the divisor latches. */
write8(&uart_ptr->lcr, line_config);
/* Enable FIFOs, and clear receive and transmit. */
write8(&uart_ptr->fcr,
UART8250_FCR_FIFO_EN | UART8250_FCR_CLEAR_RCVR |
UART8250_FCR_CLEAR_XMIT);
}
static void mtk_uart_tx_byte(unsigned char data)
{
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_THRE));
write8(&uart_ptr->thr, data);
}
static void mtk_uart_tx_flush(void)
{
while (!(read8(&uart_ptr->lsr) & UART8250_LSR_TEMT));
}
static unsigned char mtk_uart_rx_byte(void)
{
if (!mtk_uart_tst_byte())
return 0;
return read8(&uart_ptr->rbr);
}
static int mtk_uart_tst_byte(void)
{
return (read8(&uart_ptr->lsr) & UART8250_LSR_DR) == UART8250_LSR_DR;
}
void uart_init(int idx)
{
mtk_uart_init();
}
unsigned char uart_rx_byte(int idx)
{
return mtk_uart_rx_byte();
}
void uart_tx_byte(int idx, unsigned char data)
{
mtk_uart_tx_byte(data);
}
void uart_tx_flush(int idx)
{
mtk_uart_tx_flush();
}
#ifndef __PRE_RAM__
void uart_fill_lb(void *data)
{
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = UART0_BASE;
serial.baud = default_baudrate();
serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
}
#endif