google/gru: tpm on bob: cr50: add irq clear/irq status for tpm irq
BUG=b:35647967 TEST=boot from bob Change-Id: I756513f02ac13e159d5b8b1ac2346fa42cf3c219 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf18ed7b8fdf11594f812e5c48a2bd0fde5cb820 Original-Change-Id: I50c053ab7a6f6c14daee4fb2ab1cdcaeee2d67da Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/452286 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/19434 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -28,6 +28,7 @@
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#define GPIO_P15V_EN GPIO(0, B, 2)
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#define GPIO_P30V_EN GPIO(0, B, 4)
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#define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2)
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#define GPIO_TPM_IRQ GPIO(0, A, 5)
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void setup_chromeos_gpios(void);
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@ -100,6 +100,8 @@ static void configure_tpm(void)
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rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
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write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
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gpio_input_irq(GPIO_TPM_IRQ, IRQ_TYPE_EDGE_RISING);
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} else {
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gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull-up */
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gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull-up */
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@ -17,6 +17,7 @@
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#include <bootmode.h>
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#include <boot/coreboot_tables.h>
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#include <gpio.h>
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#include <tpm.h>
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#include "board.h"
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@ -35,6 +36,9 @@ void fill_lb_gpios(struct lb_gpios *gpios)
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{GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"},
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{GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"},
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{GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
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#if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
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{GPIO_TPM_IRQ.raw, ACTIVE_HIGH, -1, "TPM interrupt"},
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#endif
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};
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lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
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@ -46,3 +50,10 @@ void setup_chromeos_gpios(void)
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gpio_input_pullup(GPIO_EC_IN_RW);
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gpio_input_pullup(GPIO_EC_IRQ);
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}
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#if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
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int tis_plat_irq_status(void)
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{
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return gpio_irq_status(GPIO_TPM_IRQ);
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}
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#endif
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