GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

google/gru: tpm on bob: cr50: add irq clear/irq status for tpm irq 

BUG=b:35647967
TEST=boot from bob

Change-Id: I756513f02ac13e159d5b8b1ac2346fa42cf3c219
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf18ed7b8fdf11594f812e5c48a2bd0fde5cb820
Original-Change-Id: I50c053ab7a6f6c14daee4fb2ab1cdcaeee2d67da
Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/452286
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19434
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Jeffy Chen 2017-03-03 18:24:02 +08:00 committed by Patrick Georgi
parent b0b5987311
commit 3d966255a4
3 changed files with 14 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/gru/board.h
View File

@ -28,6 +28,7 @@
#define GPIO_P15V_EN GPIO(0, B, 2)
#define GPIO_P30V_EN GPIO(0, B, 4)
#define GPIO_P18V_AUDIO_PWREN GPIO(0, A, 2)
#define GPIO_TPM_IRQ GPIO(0, A, 5)
void setup_chromeos_gpios(void);

2
src/mainboard/google/gru/bootblock.c
View File

@ -100,6 +100,8 @@ static void configure_tpm(void)
rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz);
write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0);
gpio_input_irq(GPIO_TPM_IRQ, IRQ_TYPE_EDGE_RISING);
} else {
gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull-up */
gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull-up */

11
src/mainboard/google/gru/chromeos.c
View File

@ -17,6 +17,7 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include <tpm.h>
#include "board.h"
@ -35,6 +36,9 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"},
{GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"},
{GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
#if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
{GPIO_TPM_IRQ.raw, ACTIVE_HIGH, -1, "TPM interrupt"},
#endif
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
@ -46,3 +50,10 @@ void setup_chromeos_gpios(void)
gpio_input_pullup(GPIO_EC_IN_RW);
gpio_input_pullup(GPIO_EC_IRQ);
}
#if IS_ENABLED(CONFIG_GRU_HAS_TPM2)
int tis_plat_irq_status(void)
{
return gpio_irq_status(GPIO_TPM_IRQ);
}
#endif