From 3d96f6040901dea0b83939a9bceb49babe91c614 Mon Sep 17 00:00:00 2001 From: Tristan Shieh Date: Fri, 26 Apr 2019 11:58:30 +0800 Subject: [PATCH] mediatek: Add function to raise the CPU frequency Implement mt_pll_raise_ca53_freq() in MT8183 to raise the CPU frequency. Move the function declaration to common header. BUG=b:80501386 BRANCH=none Test=Boots correctly on Kukui Change-Id: Ide8d767486d68177fa2bfbcc5b559879eca1bcda Signed-off-by: Tristan Shieh Reviewed-on: https://review.coreboot.org/c/coreboot/+/32465 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Julius Werner --- src/soc/mediatek/common/include/soc/pll_common.h | 1 + src/soc/mediatek/mt8173/include/soc/pll.h | 1 - src/soc/mediatek/mt8173/pll.c | 3 ++- src/soc/mediatek/mt8183/Makefile.inc | 1 + src/soc/mediatek/mt8183/pll.c | 5 +++++ 5 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/soc/mediatek/common/include/soc/pll_common.h b/src/soc/mediatek/common/include/soc/pll_common.h index 480371b67c..d0ffa86c48 100644 --- a/src/soc/mediatek/common/include/soc/pll_common.h +++ b/src/soc/mediatek/common/include/soc/pll_common.h @@ -69,5 +69,6 @@ void pll_set_pcw_change(const struct pll *pll); void mux_set_sel(const struct mux *mux, u32 sel); int pll_set_rate(const struct pll *pll, u32 rate); void mt_pll_init(void); +void mt_pll_raise_ca53_freq(u32 freq); #endif diff --git a/src/soc/mediatek/mt8173/include/soc/pll.h b/src/soc/mediatek/mt8173/include/soc/pll.h index 4106d2a924..480ffbfb2d 100644 --- a/src/soc/mediatek/mt8173/include/soc/pll.h +++ b/src/soc/mediatek/mt8173/include/soc/pll.h @@ -292,7 +292,6 @@ enum { void mt_pll_post_init(void); void mt_pll_set_aud_div(u32 rate); void mt_pll_enable_ssusb_clk(void); -void mt_pll_raise_ca53_freq(u32 freq); void mt_mem_pll_set_clk_cfg(void); void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params); void mt_mem_pll_config_post(void); diff --git a/src/soc/mediatek/mt8173/pll.c b/src/soc/mediatek/mt8173/pll.c index c59fa3f528..7eb12b1282 100644 --- a/src/soc/mediatek/mt8173/pll.c +++ b/src/soc/mediatek/mt8173/pll.c @@ -432,7 +432,8 @@ void mt_pll_set_aud_div(u32 rate) } } -void mt_pll_raise_ca53_freq(u32 freq) { +void mt_pll_raise_ca53_freq(u32 freq) +{ pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */ } diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 3fce0a81fd..5392a9e635 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -32,6 +32,7 @@ romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c romstage-y += mt8183.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c +romstage-y += ../common/pll.c pll.c romstage-y += ../common/pmic_wrap.c pmic_wrap.c mt6358.c romstage-y += ../common/rtc.c rtc.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8183/pll.c b/src/soc/mediatek/mt8183/pll.c index 8608b4ac10..07ce6603f6 100644 --- a/src/soc/mediatek/mt8183/pll.c +++ b/src/soc/mediatek/mt8183/pll.c @@ -369,3 +369,8 @@ void mt_pll_init(void) /* enable mtkaif 26m clock */ setbits_le32(&mt8183_infracfg->module_sw_cg_2_clr, 1 << 4); } + +void mt_pll_raise_ca53_freq(u32 freq) +{ + pll_set_rate(&plls[APMIXED_ARMPLL_LL], freq); +}