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Supermicro H8QGI: Substract 1 from MMCONF range limit 

MMCONF space is defined by two config parameters:
MMCONF_BASE_ADDRESS (0xF800 0000)
MMCONF_BUS_NUMBER (64)

Coreboot allocates 1MB per bus, so MMCONF limit should be:
0xF800 0000 + 64*(0x0010 0000) - 1 = 0xFBFF FFFF

Current code does not have (-1) component, this makes MMCONF limit
equal 0xFC00 FFFF. Not 0xFC00 0000, because according to BKDG
lower two bytes of MMIO limit always equal 0xFFFF:
MMIOLimit = {MMIOLimitRegister[47:16], FFFFh}.

Add (-1) to correct this issue.

No functionality change has been experienced. The five times
slower RAM speed compared to the proprietary vendor BIOS still
remains.

Change-Id: I2c6494c28bb8d36e54ceb2aa7d8d965b0103cbe9
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2193
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
Konstantin Aladyshev 2013-01-25 19:20:51 +04:00 committed by Patrick Georgi
parent 96e3035a1f
commit 3d990ffc88
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/supermicro/h8qgi/agesawrapper.c
View File

@ -147,7 +147,7 @@ static UINT32 agesawrapper_amdinitcpuio(VOID)
* coreboot not implemente the range by range setting yet.
*/
PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB + node, FUNC_1, 0xBC);
PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000);//1MB each bus
PciData = CONFIG_MMCONF_BASE_ADDRESS + (CONFIG_MMCONF_BUS_NUMBER * 0x100000) - 1;//1MB each bus
PciData = (PciData >> 8) & 0xFFFFFF00;
PciData |= 0x80; //NP
PciData |= sblink << 4;