bd82x6x: Consolidate early native USB init
Change-Id: I6189930fd3c69c3497e4cf1a78035e6614761b13 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6923 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
parent
cb0d772eef
commit
3dc12c1e19
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@ -110,45 +110,6 @@ static void rcba_config(void)
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RCBA32(BUC) = 0;
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RCBA32(BUC) = 0;
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}
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}
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static void init_usb(void)
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{
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const u32 rcba_dump[64] = {
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/* 3500 */ 0x20000f57, 0x20000f57, 0x2000055b, 0x20000f57,
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/* 3510 */ 0x20000f57, 0x20000153, 0x20000153, 0x2000055b,
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/* 3520 */ 0x20000153, 0x20000f57, 0x20000153, 0x20000153,
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/* 3530 */ 0x20000f51, 0x20000f57, 0x00000000, 0x00000000,
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/* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
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/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
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/* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00001448,
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/* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000,
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/* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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};
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int i;
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/* Activate PMBAR. */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
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/* Unlock registers. */
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outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
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for (i = 0; i < 64; i++)
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write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
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pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
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/* Relock registers. */
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outw (0x0000, DEFAULT_PMBASE | 0x003c);
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}
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void main(unsigned long bist)
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void main(unsigned long bist)
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{
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{
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int s3resume = 0;
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int s3resume = 0;
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@ -184,7 +145,22 @@ void main(unsigned long bist)
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outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3);
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outl(0x00000fff, DEFAULT_GPIOBASE + GP_IO_SEL3);
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outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3);
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outl(0x00000f4f, DEFAULT_GPIOBASE + GP_LVL3);
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init_usb();
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early_usb_init((struct southbridge_usb_port []) {
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{ 1, 1, 0 },
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{ 1, 1, 1 },
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{ 1, 2, 3 },
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{ 1, 1, -1 },
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{ 1, 1, -1 },
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{ 1, 0, -1 },
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{ 0, 0, -1 },
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{ 1, 2, -1 },
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{ 1, 0, -1 },
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{ 1, 1, 5 },
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{ 1, 0, -1 },
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{ 1, 0, -1 },
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{ 1, 3, -1 },
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{ 1, 1, -1 },
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});
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/* Initialize console device(s) */
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/* Initialize console device(s) */
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console_init();
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console_init();
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@ -105,45 +105,6 @@ static void rcba_config(void)
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RCBA32(BUC) = 0;
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RCBA32(BUC) = 0;
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}
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}
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static void
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init_usb (void)
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{
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const u32 rcba_dump[64] = {
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/* 3500 */ 0x20000153, 0x20000f57, 0x20000f57, 0x20000f57,
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/* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x20000153,
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/* 3520 */ 0x20000f57, 0x20000f57, 0x20000f57, 0x20000f57,
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/* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000,
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/* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3560 */ 0x020c0001, 0x000024a3, 0x00040002, 0x01000050,
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/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
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/* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3590 */ 0x00000003, 0x000000c0, 0x00000000, 0x00000000,
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/* 35a0 */ 0x0fc00201, 0x102d0200, 0x00000000, 0x00000000,
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/* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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};
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int i;
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/* Activate PMBAR. */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
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/* Unlock registers. */
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outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
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for (i = 0; i < 64; i++)
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write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
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pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
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/* Relock registers. */
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outw (0x0000, DEFAULT_PMBASE | 0x003c);
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}
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#include <cpu/intel/romstage.h>
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#include <cpu/intel/romstage.h>
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void main(unsigned long bist)
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void main(unsigned long bist)
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{
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{
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@ -179,7 +140,22 @@ void main(unsigned long bist)
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outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44);
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outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44);
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outl(0x00000fcf, DEFAULT_GPIOBASE + 0x48);
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outl(0x00000fcf, DEFAULT_GPIOBASE + 0x48);
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init_usb();
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early_usb_init((struct southbridge_usb_port []) {
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{ 1, 0, 0 },
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{ 1, 1, 1 },
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{ 1, 1, 3 },
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{ 1, 1, 3 },
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{ 1, 1, -1 },
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{ 1, 1, -1 },
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{ 1, 0, 2 },
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{ 1, 0, 2 },
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{ 1, 1, 6 },
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{ 1, 1, 5 },
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{ 1, 1, 6 },
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{ 1, 1, 6 },
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{ 1, 1, 7 },
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{ 1, 1, 6 },
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});
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/* Initialize console device(s) */
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/* Initialize console device(s) */
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console_init();
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console_init();
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@ -109,45 +109,6 @@ static void rcba_config(void)
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RCBA32(BUC) = 0;
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RCBA32(BUC) = 0;
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}
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}
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static void
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init_usb (void)
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{
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const u32 rcba_dump[64] = {
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/* 3500 */ 0x20000153, 0x20000153, 0x20000f57, 0x20000f57,
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/* 3510 */ 0x20000f57, 0x20000f57, 0x20000153, 0x2000055b,
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/* 3520 */ 0x20000153, 0x2000055b, 0x20000f57, 0x20000f57,
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/* 3530 */ 0x20000f57, 0x20000f57, 0x00000000, 0x00000000,
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/* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
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/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
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/* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000040,
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/* 35a0 */ 0x04000201, 0x00000200, 0x00000000, 0x00000000,
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/* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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/* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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};
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int i;
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/* Activate PMBAR. */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
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/* Unlock registers. */
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outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
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for (i = 0; i < 64; i++)
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write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i), rcba_dump[i]);
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pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
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/* Relock registers. */
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outw (0x0000, DEFAULT_PMBASE | 0x003c);
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}
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#include <cpu/intel/romstage.h>
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#include <cpu/intel/romstage.h>
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void main(unsigned long bist)
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void main(unsigned long bist)
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{
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{
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@ -173,7 +134,22 @@ void main(unsigned long bist)
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setup_pch_gpios(&x230_gpio_map);
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setup_pch_gpios(&x230_gpio_map);
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init_usb();
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early_usb_init((struct southbridge_usb_port []) {
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{ 1, 0, 0 }, /* P0 (left, fan side), OC 0 */
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{ 1, 0, 1 }, /* P1 (left touchpad side), OC 1 */
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{ 1, 1, 3 }, /* P2: dock, OC 3 */
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{ 1, 1, -1 }, /* P3: wwan, no OC */
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{ 1, 1, -1 }, /* P4: Wacom tablet on X230t, otherwise empty */
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{ 1, 1, -1 }, /* P5: Expresscard, no OC */
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{ 0, 0, -1 }, /* P6: Empty */
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{ 1, 2, -1 }, /* P7: dock, no OC */
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{ 1, 0, -1 },
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{ 1, 2, 5 }, /* P9: Right (EHCI debug), OC 5 */
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{ 1, 1, -1 }, /* P10: fingerprint reader, no OC */
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{ 1, 1, -1 }, /* P11: bluetooth, no OC. */
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{ 1, 1, -1 }, /* P12: wlan, no OC */
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{ 1, 1, -1 }, /* P13: webcam, no OC */
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});
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/* Initialize console device(s) */
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/* Initialize console device(s) */
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console_init();
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console_init();
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@ -47,14 +47,14 @@ smm-$(CONFIG_SPI_FLASH_SMM) += ../common/spi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c pch.c
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romstage-y += early_usb.c early_smbus.c me_status.c gpio.c
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romstage-y += early_smbus.c me_status.c gpio.c
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romstage-y += reset.c
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romstage-y += reset.c
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romstage-y += early_spi.c early_pch.c
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romstage-y += early_spi.c early_pch.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += early_me.c early_usb.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += early_me.c early_usb.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c
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romstage-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE) += early_thermal.c early_pch_native.c early_me_native.c early_usb_native.c
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
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IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
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@ -0,0 +1,77 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Vladimir Serbinenko
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/console.h>
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#include <device/pci_ids.h>
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#include <device/pci_def.h>
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#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */
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#include "pch.h"
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void
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early_usb_init (const struct southbridge_usb_port *portmap)
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{
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u32 reg32;
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const u32 rcba_dump[8] = {
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/* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050,
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/* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630,
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};
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const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 };
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int i;
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/* Activate PMBAR. */
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
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pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
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pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
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/* Unlock registers. */
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outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
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for (i = 0; i < 14; i++)
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write32 (DEFAULT_RCBABASE | (0x3500 + 4 * i),
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currents[portmap[i].current]);
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for (i = 0; i < 10; i++)
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write32 (DEFAULT_RCBABASE | (0x3538 + 4 * i), 0);
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for (i = 0; i < 8; i++)
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write32 (DEFAULT_RCBABASE | (0x3560 + 4 * i), rcba_dump[i]);
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for (i = 0; i < 8; i++)
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write32 (DEFAULT_RCBABASE | (0x3580 + 4 * i), 0);
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reg32 = 0;
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for (i = 0; i < 14; i++)
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if (!portmap[i].enabled)
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reg32 |= (1 << i);
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||||||
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write32 (DEFAULT_RCBABASE | 0x359c, reg32);
|
||||||
|
reg32 = 0;
|
||||||
|
for (i = 0; i < 8; i++)
|
||||||
|
if (portmap[i].enabled && portmap[i].oc_pin >= 0)
|
||||||
|
reg32 |= (1 << (i + 8 * portmap[i].oc_pin));
|
||||||
|
write32 (DEFAULT_RCBABASE | 0x35a0, reg32);
|
||||||
|
reg32 = 0;
|
||||||
|
for (i = 8; i < 14; i++)
|
||||||
|
if (portmap[i].enabled && portmap[i].oc_pin >= 4)
|
||||||
|
reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4)));
|
||||||
|
write32 (DEFAULT_RCBABASE | 0x35a4, reg32);
|
||||||
|
for (i = 0; i < 22; i++)
|
||||||
|
write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0);
|
||||||
|
|
||||||
|
pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
|
||||||
|
|
||||||
|
/* Relock registers. */
|
||||||
|
outw (0x0000, DEFAULT_PMBASE | 0x003c);
|
||||||
|
}
|
|
@ -77,6 +77,17 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
|
||||||
void early_thermal_init(void);
|
void early_thermal_init(void);
|
||||||
void early_pch_init_native(void);
|
void early_pch_init_native(void);
|
||||||
int southbridge_detect_s3_resume(void);
|
int southbridge_detect_s3_resume(void);
|
||||||
|
|
||||||
|
struct southbridge_usb_port
|
||||||
|
{
|
||||||
|
int enabled;
|
||||||
|
int current;
|
||||||
|
int oc_pin;
|
||||||
|
};
|
||||||
|
|
||||||
|
void
|
||||||
|
early_usb_init (const struct southbridge_usb_port *portmap);
|
||||||
|
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
|
Loading…
Reference in New Issue