ChromeOS: Separate NVS from global GNVS

Allocate chromeos_acpi in CBMEM separately from GNVS.

Change-Id: Ide55964ed53ea1d5b3c1c4e3ebd67286b7d568e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/acpi/acpi.c

@@ -1704,6 +1704,8 @@ unsigned long write_acpi_tables(unsigned long start)
 
 		if (CONFIG(ACPI_SOC_NVS))
 			acpi_fill_gnvs();
+		if (CONFIG(CHROMEOS_NVS))
+			acpi_fill_cnvs();
 
 		for (dev = all_devices; dev; dev = dev->next)
 			if (dev->ops && dev->ops->acpi_inject_dsdt)

src/acpi/gnvs.c

@@ -37,11 +37,6 @@ void acpi_create_gnvs(void)
 
 	if (CONFIG(CONSOLE_CBMEM))
 		gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
-
-	if (CONFIG(CHROMEOS_NVS)) {
-		chromeos_acpi_t *init = (void *)((u8 *)gnvs + GNVS_CHROMEOS_ACPI_OFFSET);
-		chromeos_init_chromeos_acpi(init);
-	}
 }
 
 void *acpi_get_gnvs(void)
@@ -70,8 +65,6 @@ __weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { }
 void acpi_fill_gnvs(void)
 {
 	const struct opregion gnvs_op = OPREGION("GNVS", SYSTEMMEMORY, (uintptr_t)gnvs, 0x100);
-	const struct opregion cnvs_op =	OPREGION("CNVS", SYSTEMMEMORY,
-					(uintptr_t)gnvs + GNVS_CHROMEOS_ACPI_OFFSET, 0xf00);
 	const struct opregion dnvs_op = OPREGION("DNVS", SYSTEMMEMORY,
 					(uintptr_t)gnvs + GNVS_DEVICE_NVS_OFFSET, 0x1000);
 
@@ -84,9 +77,6 @@ void acpi_fill_gnvs(void)
 	acpigen_write_scope("\\");
 	acpigen_write_opregion(&gnvs_op);
 
-	if (CONFIG(CHROMEOS_NVS))
-		acpigen_write_opregion(&cnvs_op);
-
 	if (CONFIG(ACPI_HAS_DEVICE_NVS))
 		acpigen_write_opregion(&dnvs_op);
 

src/commonlib/include/commonlib/cbmem_id.h

@@ -5,6 +5,7 @@
 
 #define CBMEM_ID_ACPI		0x41435049
 #define CBMEM_ID_ACPI_BERT      0x42455254
+#define CBMEM_ID_ACPI_CNVS	0x434e5653
 #define CBMEM_ID_ACPI_GNVS	0x474e5653
 #define CMBMEM_ID_ACPI_HEST	0x48455354
 #define CBMEM_ID_ACPI_UCSI	0x55435349
@@ -81,6 +82,7 @@
 #define CBMEM_ID_TO_NAME_TABLE				 \
 	{ CBMEM_ID_ACPI,		"ACPI       " }, \
 	{ CBMEM_ID_ACPI_BERT,		"ACPI BERT  " }, \
+	{ CBMEM_ID_ACPI_CNVS,		"CHROMEOS NVS" }, \
 	{ CBMEM_ID_ACPI_GNVS,		"ACPI GNVS  " }, \
 	{ CMBMEM_ID_ACPI_HEST,		"ACPI HEST  " }, \
 	{ CBMEM_ID_ACPI_UCSI,		"ACPI UCSI  " }, \

src/include/acpi/acpi.h

@@ -1209,6 +1209,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt);
 void mainboard_fill_fadt(acpi_fadt_t *fadt);
 
 void acpi_fill_gnvs(void);
+void acpi_fill_cnvs(void);
 
 void update_ssdt(void *ssdt);
 void update_ssdtx(void *ssdtx, int i);

src/lib/hardwaremain.c

@@ -24,6 +24,7 @@
 #include <timer.h>
 #include <timestamp.h>
 #include <thread.h>
+#include <vendorcode/google/chromeos/gnvs.h>
 
 static boot_state_t bs_pre_device(void *arg);
 static boot_state_t bs_dev_init_chips(void *arg);
@@ -461,6 +462,9 @@ void main(void)
 	if (CONFIG(ACPI_SOC_NVS))
 		acpi_create_gnvs();
 
+	if (CONFIG(CHROMEOS_NVS))
+		chromeos_init_chromeos_acpi();
+
 	/* Schedule the static boot state entries. */
 	boot_state_schedule_static_entries();
 

src/vendorcode/google/chromeos/gnvs.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <acpi/acpi_gnvs.h>
+#include <acpi/acpi.h>
+#include <acpi/acpigen.h>
 #include <types.h>
 #include <string.h>
 #include <stdlib.h>
@@ -16,7 +17,7 @@
 #include "chromeos.h"
 #include "gnvs.h"
 
-static chromeos_acpi_t *chromeos_acpi;
+static struct chromeos_acpi *chromeos_acpi;
 
 static size_t chromeos_vpd_region(const char *region, uintptr_t *base)
 {
@@ -30,12 +31,14 @@ static size_t chromeos_vpd_region(const char *region, uintptr_t *base)
 	return region_device_sz(&vpd);
 }
 
-void chromeos_init_chromeos_acpi(chromeos_acpi_t *init)
+void chromeos_init_chromeos_acpi(void)
 {
 	size_t vpd_size;
 	uintptr_t vpd_base = 0;
 
-	chromeos_acpi = init;
+	chromeos_acpi = cbmem_add(CBMEM_ID_ACPI_CNVS, sizeof(struct chromeos_acpi));
+	if (!chromeos_acpi)
+		return;
 
 	vpd_size = chromeos_vpd_region("RO_VPD", &vpd_base);
 	if (vpd_size && vpd_base) {
@@ -90,3 +93,12 @@ void smbios_type0_bios_version(uintptr_t address)
 	/* Location of smbios_type0.bios_version() string filled with spaces. */
 	chromeos_acpi->vbt10 = address;
 }
+
+void acpi_fill_cnvs(void)
+{
+	const struct opregion cnvs_op = OPREGION("CNVS", SYSTEMMEMORY, (uintptr_t)chromeos_acpi,
+						 sizeof(*chromeos_acpi));
+	acpigen_write_scope("\\");
+	acpigen_write_opregion(&cnvs_op);
+	acpigen_pop_len();
+}

src/vendorcode/google/chromeos/gnvs.h

@@ -8,16 +8,9 @@
 #define ACTIVE_ECFW_RO		0
 #define ACTIVE_ECFW_RW		1
 
-/*
- * chromeos_acpi_t portion of ACPI GNVS is assumed to live at
- * 0x100 - 0x1000.
- */
-#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
-
-/* device_nvs_t is assumed to live directly after chromeos_acpi_t. */
 #define GNVS_DEVICE_NVS_OFFSET 0x1000
 
-typedef struct {
+struct chromeos_acpi {
 	/* ChromeOS specific */
 	u32	vbt0;		// 00 boot reason
 	u32	vbt1;		// 04 active main firmware
@@ -39,8 +32,8 @@ typedef struct {
 	u32	vpd_rw_base;	// dce pointer to RW_VPD
 	u32	vpd_rw_size;	// dd2 size of RW_VPD
 	u8	pad[298];	// dd6-eff
-} __packed chromeos_acpi_t;
+} __packed;
 
-void chromeos_init_chromeos_acpi(chromeos_acpi_t *init);
+void chromeos_init_chromeos_acpi(void);
 
 #endif