soc/intel/cnl: Set Heci1Disable depending on devicetree config
Currently HECI1 gets enabled by the option HeciEnabled, but this duplicates the devicetree on/off options. Therefore use the on/off options for the enablement/disablement of the HECI1 device. All corresponding mainboards were checked if the devicetree matches the HeciEnabled setting, and adjusted where necessary. Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5 Signed-off-by: Felix Singer <felix.singer@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
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@ -30,7 +30,6 @@ chip soc/intel/cannonlake
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# FSP configuration
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# FSP configuration
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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register "HeciEnabled" = "0"
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register "InternalGfx" = "1"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "SkipExtGfxScan" = "1"
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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register "PchPmSlpS3MinAssert" = "3" # 50ms
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@ -418,7 +417,7 @@ chip soc/intel/cannonlake
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end # I2C #1
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end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -29,8 +29,6 @@ chip soc/intel/cannonlake
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register "satapwroptimize" = "1"
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register "satapwroptimize" = "1"
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# Enable System Agent dynamic frequency
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# Enable System Agent dynamic frequency
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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# Enable heci communication
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register "HeciEnabled" = "0"
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# Enable Speed Shift Technology support
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# Enable Speed Shift Technology support
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register "speed_shift_enable" = "1"
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register "speed_shift_enable" = "1"
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# Enable S0ix
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# Enable S0ix
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@ -312,7 +310,7 @@ chip soc/intel/cannonlake
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device pci 15.1 on end # I2C #1
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device pci 15.1 on end # I2C #1
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device pci 15.2 on end # I2C #2
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device pci 15.2 on end # I2C #2
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device pci 15.3 on end # I2C #3
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device pci 15.3 on end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -1,6 +1,4 @@
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chip soc/intel/cannonlake
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chip soc/intel/cannonlake
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# Enable heci communication
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register "HeciEnabled" = "1"
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# Auto-switch between X4 NVMe and X2 NVMe.
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# Auto-switch between X4 NVMe and X2 NVMe.
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register "TetonGlacierMode" = "1"
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register "TetonGlacierMode" = "1"
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@ -369,6 +367,7 @@ chip soc/intel/cannonlake
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device i2c 4a on end
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device i2c 4a on end
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end
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end
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end # I2C #3, Realtek RTD2142.
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end # I2C #3, Realtek RTD2142.
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device pci 16.0 on end # Management Engine Interface 1
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device pci 19.0 on
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device pci 19.0 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "hid" = ""10EC5682""
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@ -1,6 +1,4 @@
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chip soc/intel/cannonlake
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chip soc/intel/cannonlake
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# Enable heci communication
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register "HeciEnabled" = "1"
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# Auto-switch between X4 NVMe and X2 NVMe.
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# Auto-switch between X4 NVMe and X2 NVMe.
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register "TetonGlacierMode" = "1"
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register "TetonGlacierMode" = "1"
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@ -376,6 +374,7 @@ chip soc/intel/cannonlake
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device i2c 4a on end
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device i2c 4a on end
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end
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end
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end # I2C #3, Realtek RTD2142.
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end # I2C #3, Realtek RTD2142.
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device pci 16.0 on end # Management Engine Interface 1
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device pci 19.0 on
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device pci 19.0 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "hid" = ""10EC5682""
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@ -1,6 +1,4 @@
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chip soc/intel/cannonlake
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chip soc/intel/cannonlake
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# Enable heci communication
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register "HeciEnabled" = "1"
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# Auto-switch between X4 NVMe and X2 NVMe.
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# Auto-switch between X4 NVMe and X2 NVMe.
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register "TetonGlacierMode" = "1"
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register "TetonGlacierMode" = "1"
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@ -369,6 +367,7 @@ chip soc/intel/cannonlake
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device i2c 4a on end
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device i2c 4a on end
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end
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end
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end # I2C #3, Realtek RTD2142.
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end # I2C #3, Realtek RTD2142.
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device pci 16.0 on end # Management Engine Interface 1
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device pci 19.0 on
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device pci 19.0 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "hid" = ""10EC5682""
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@ -1,6 +1,4 @@
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chip soc/intel/cannonlake
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chip soc/intel/cannonlake
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# Enable heci communication
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register "HeciEnabled" = "1"
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# Auto-switch between X4 NVMe and X2 NVMe.
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# Auto-switch between X4 NVMe and X2 NVMe.
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register "TetonGlacierMode" = "1"
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register "TetonGlacierMode" = "1"
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@ -284,6 +282,7 @@ chip soc/intel/cannonlake
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device i2c 4a on end
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device i2c 4a on end
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end
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end
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end # I2C #3, Realtek RTD2142.
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end # I2C #3, Realtek RTD2142.
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device pci 16.0 on end # Management Engine Interface 1
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device pci 19.0 on
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device pci 19.0 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "hid" = ""10EC5682""
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@ -1,6 +1,4 @@
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chip soc/intel/cannonlake
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chip soc/intel/cannonlake
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# Enable heci communication
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register "HeciEnabled" = "1"
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# Auto-switch between X4 NVMe and X2 NVMe.
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# Auto-switch between X4 NVMe and X2 NVMe.
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register "TetonGlacierMode" = "1"
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register "TetonGlacierMode" = "1"
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@ -308,6 +306,7 @@ chip soc/intel/cannonlake
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device i2c 4a on end
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device i2c 4a on end
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end
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end
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end # I2C #3, Realtek RTD2142.
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end # I2C #3, Realtek RTD2142.
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device pci 16.0 on end # Management Engine Interface 1
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device pci 19.0 on
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device pci 19.0 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "hid" = ""10EC5682""
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@ -1,6 +1,4 @@
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chip soc/intel/cannonlake
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chip soc/intel/cannonlake
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# Enable heci communication
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register "HeciEnabled" = "1"
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# Auto-switch between X4 NVMe and X2 NVMe.
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# Auto-switch between X4 NVMe and X2 NVMe.
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register "TetonGlacierMode" = "1"
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register "TetonGlacierMode" = "1"
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@ -303,6 +301,7 @@ chip soc/intel/cannonlake
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device i2c 4a on end
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device i2c 4a on end
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end
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end
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end # I2C #3, Realtek RTD2142.
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end # I2C #3, Realtek RTD2142.
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device pci 16.0 on end # Management Engine Interface 1
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device pci 19.0 on
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device pci 19.0 on
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chip drivers/i2c/generic
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chip drivers/i2c/generic
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register "hid" = ""10EC5682""
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register "hid" = ""10EC5682""
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@ -15,7 +15,6 @@ chip soc/intel/cannonlake
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# FSP configuration
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# FSP configuration
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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register "HeciEnabled" = "0"
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register "SataSalpSupport" = "1"
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register "SataSalpSupport" = "1"
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register "SataMode" = "Sata_AHCI"
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register "SataMode" = "Sata_AHCI"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsEnable[2]" = "1"
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@ -350,7 +349,7 @@ chip soc/intel/cannonlake
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end # I2C #1
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end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -15,7 +15,6 @@ chip soc/intel/cannonlake
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# FSP configuration
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# FSP configuration
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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register "HeciEnabled" = "0"
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register "SataSalpSupport" = "1"
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register "SataSalpSupport" = "1"
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register "SataMode" = "Sata_AHCI"
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register "SataMode" = "Sata_AHCI"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[0]" = "1"
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@ -369,7 +368,7 @@ chip soc/intel/cannonlake
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end # I2C #1
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end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -8,9 +8,6 @@ chip soc/intel/cannonlake
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register "SaGv" = "SaGv_Enabled"
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register "SaGv" = "SaGv_Enabled"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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# HECI
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register "HeciEnabled" = "1"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
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register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"
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@ -197,9 +197,7 @@ chip soc/intel/cannonlake
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device pci 15.1 off end # I2C #1
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 15.3 off end # I2C #3
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device pci 16.0 off # Management Engine Interface 1
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device pci 16.0 off end # Management Engine Interface 1
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register "HeciEnabled" = "0"
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end
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.3 off end # Management Engine KT Redirection
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@ -525,7 +525,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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params->Heci3Enabled = config->Heci3Enabled;
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params->Heci3Enabled = config->Heci3Enabled;
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#if !CONFIG(HECI_DISABLE_USING_SMM)
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#if !CONFIG(HECI_DISABLE_USING_SMM)
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params->Heci1Disabled = !config->HeciEnabled;
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dev = pcidev_path_on_root(PCH_DEVFN_CSE);
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params->Heci1Disabled = !is_dev_enabled(dev);
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#endif
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#endif
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params->Device4Enable = config->Device4Enable;
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params->Device4Enable = config->Device4Enable;
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