soc/intel/cnl: Set Heci1Disable depending on devicetree config

Currently HECI1 gets enabled by the option HeciEnabled, but this
duplicates the devicetree on/off options. Therefore use the on/off
options for the enablement/disablement of the HECI1 device.

All corresponding mainboards were checked if the devicetree matches
the HeciEnabled setting, and adjusted where necessary.

Change-Id: I03dd3577fbe3f68b0abc2d196d016a4d26d88ce5
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner

src/mainboard/google/drallion/variants/drallion/devicetree.cb

@@ -30,7 +30,6 @@ chip soc/intel/cannonlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
-	register "HeciEnabled" = "0"
 	register "InternalGfx" = "1"
 	register "SkipExtGfxScan" = "1"
 	register "PchPmSlpS3MinAssert" = "3"  # 50ms
@@ -418,7 +417,7 @@ chip soc/intel/cannonlake
 		end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.0 off end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/mainboard/google/hatch/variants/baseboard/devicetree.cb

@@ -29,8 +29,6 @@ chip soc/intel/cannonlake
 	register "satapwroptimize" = "1"
 	# Enable System Agent dynamic frequency
 	register "SaGv" = "SaGv_Enabled"
-	# Enable heci communication
-	register "HeciEnabled" = "0"
 	# Enable Speed Shift Technology support
 	register "speed_shift_enable" = "1"
 	# Enable S0ix
@@ -312,7 +310,7 @@ chip soc/intel/cannonlake
 		device pci 15.1 on  end # I2C #1
 		device pci 15.2 on  end # I2C #2
 		device pci 15.3 on  end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.0 off end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/mainboard/google/hatch/variants/duffy/overridetree.cb

@@ -1,6 +1,4 @@
 chip soc/intel/cannonlake
-	# Enable heci communication
-	register "HeciEnabled" = "1"
 
 	# Auto-switch between X4 NVMe and X2 NVMe.
 	register "TetonGlacierMode" = "1"
@@ -369,6 +367,7 @@ chip soc/intel/cannonlake
 				device i2c 4a on end
 			end
 		end # I2C #3, Realtek RTD2142.
+		device pci 16.0 on end # Management Engine Interface 1
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

src/mainboard/google/hatch/variants/faffy/overridetree.cb

@@ -1,6 +1,4 @@
 chip soc/intel/cannonlake
-	# Enable heci communication
-	register "HeciEnabled" = "1"
 
 	# Auto-switch between X4 NVMe and X2 NVMe.
 	register "TetonGlacierMode" = "1"
@@ -376,6 +374,7 @@ chip soc/intel/cannonlake
 				device i2c 4a on end
 			end
 		end # I2C #3, Realtek RTD2142.
+		device pci 16.0 on end # Management Engine Interface 1
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

src/mainboard/google/hatch/variants/kaisa/overridetree.cb

@@ -1,6 +1,4 @@
 chip soc/intel/cannonlake
-	# Enable heci communication
-	register "HeciEnabled" = "1"
 
 	# Auto-switch between X4 NVMe and X2 NVMe.
 	register "TetonGlacierMode" = "1"
@@ -369,6 +367,7 @@ chip soc/intel/cannonlake
 				device i2c 4a on end
 			end
 		end # I2C #3, Realtek RTD2142.
+		device pci 16.0 on end # Management Engine Interface 1
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

src/mainboard/google/hatch/variants/noibat/overridetree.cb

@@ -1,6 +1,4 @@
 chip soc/intel/cannonlake
-	# Enable heci communication
-	register "HeciEnabled" = "1"
 
 	# Auto-switch between X4 NVMe and X2 NVMe.
 	register "TetonGlacierMode" = "1"
@@ -284,6 +282,7 @@ chip soc/intel/cannonlake
 				device i2c 4a on end
 			end
 		end # I2C #3, Realtek RTD2142.
+		device pci 16.0 on end # Management Engine Interface 1
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

src/mainboard/google/hatch/variants/puff/overridetree.cb

@@ -1,6 +1,4 @@
 chip soc/intel/cannonlake
-	# Enable heci communication
-	register "HeciEnabled" = "1"
 
 	# Auto-switch between X4 NVMe and X2 NVMe.
 	register "TetonGlacierMode" = "1"
@@ -308,6 +306,7 @@ chip soc/intel/cannonlake
 				device i2c 4a on end
 			end
 		end # I2C #3, Realtek RTD2142.
+		device pci 16.0 on end # Management Engine Interface 1
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

src/mainboard/google/hatch/variants/wyvern/overridetree.cb

@@ -1,6 +1,4 @@
 chip soc/intel/cannonlake
-	# Enable heci communication
-	register "HeciEnabled" = "1"
 
 	# Auto-switch between X4 NVMe and X2 NVMe.
 	register "TetonGlacierMode" = "1"
@@ -303,6 +301,7 @@ chip soc/intel/cannonlake
 				device i2c 4a on end
 			end
 		end # I2C #3, Realtek RTD2142.
+		device pci 16.0 on end # Management Engine Interface 1
 		device pci 19.0 on
 			chip drivers/i2c/generic
 				register "hid" = ""10EC5682""

src/mainboard/google/sarien/variants/arcada/devicetree.cb

@@ -15,7 +15,6 @@ chip soc/intel/cannonlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
-	register "HeciEnabled" = "0"
 	register "SataSalpSupport" = "1"
 	register "SataMode" = "Sata_AHCI"
 	register "SataPortsEnable[2]" = "1"
@@ -350,7 +349,7 @@ chip soc/intel/cannonlake
 		end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.0 off end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/mainboard/google/sarien/variants/sarien/devicetree.cb

@@ -15,7 +15,6 @@ chip soc/intel/cannonlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
-	register "HeciEnabled" = "0"
 	register "SataSalpSupport" = "1"
 	register "SataMode" = "Sata_AHCI"
 	register "SataPortsEnable[0]" = "1"
@@ -369,7 +368,7 @@ chip soc/intel/cannonlake
 		end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 on  end # Management Engine Interface 1
+		device pci 16.0 off end # Management Engine Interface 1
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb

@@ -8,9 +8,6 @@ chip soc/intel/cannonlake
 	register "SaGv" = "SaGv_Enabled"
 	register "ScsEmmcHs400Enabled" = "1"
 
-	# HECI
-	register "HeciEnabled" = "1"
-
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
 	register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC0)"

src/mainboard/system76/lemp9/devicetree.cb

@@ -197,9 +197,7 @@ chip soc/intel/cannonlake
 		device pci 15.1 off end # I2C #1
 		device pci 15.2 off end # I2C #2
 		device pci 15.3 off end # I2C #3
-		device pci 16.0 off     # Management Engine Interface 1
+		device pci 16.0 off end # Management Engine Interface 1
-			register "HeciEnabled" = "0"
-		end
 		device pci 16.1 off end # Management Engine Interface 2
 		device pci 16.2 off end # Management Engine IDE-R
 		device pci 16.3 off end # Management Engine KT Redirection

src/soc/intel/cannonlake/fsp_params.c

@@ -525,7 +525,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	params->Heci3Enabled = config->Heci3Enabled;
 #if !CONFIG(HECI_DISABLE_USING_SMM)
-	params->Heci1Disabled = !config->HeciEnabled;
+	dev = pcidev_path_on_root(PCH_DEVFN_CSE);
+	params->Heci1Disabled = !is_dev_enabled(dev);
 #endif
 	params->Device4Enable = config->Device4Enable;