diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c
index 985f2c4814..27870b0cf7 100644
--- a/src/soc/intel/common/block/systemagent/memmap.c
+++ b/src/soc/intel/common/block/systemagent/memmap.c
@@ -6,6 +6,7 @@
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/smm.h>
 #include <intelblocks/systemagent.h>
+#include <types.h>
 
 /*
  * Expected Host Memory Map (we don't know 100% and not all regions are present on all SoCs):
@@ -55,18 +56,18 @@ void smm_region(uintptr_t *start, size_t *size)
 
 void fill_postcar_frame(struct postcar_frame *pcf)
 {
-	uintptr_t top_of_ram;
+	/* FSP does not seem to bother w.r.t. alignment when asked to place cbmem_top() */
+	uintptr_t top_of_ram = ALIGN_UP((uintptr_t)cbmem_top(), 8 * MiB);
 
 	/*
 	 * We need to make sure ramstage will be run cached. At this
 	 * point exact location of ramstage in cbmem is not known.
-	 * Instruct postcar to cache 16 megs under cbmem top which is
+	 * Instruct postcar to cache 16 megs below cbmem top which is
 	 * a safe bet to cover ramstage.
 	 */
-	top_of_ram = (uintptr_t) cbmem_top();
 	printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
-	top_of_ram -= 16*MiB;
-	postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+	postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK);
 
 	/* Cache the TSEG region */
 	postcar_enable_tseg_cache(pcf);