diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c
index 1741ae6b82..c026004eaf 100644
--- a/src/soc/intel/broadwell/romstage/romstage.c
+++ b/src/soc/intel/broadwell/romstage/romstage.c
@@ -38,6 +38,7 @@
 #include <soc/reset.h>
 #include <soc/romstage.h>
 #include <soc/spi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Entry from cache-as-ram.inc. */
 void * asmlinkage romstage_main(unsigned long bist,
diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c
index a151f54619..72163732c2 100644
--- a/src/vendorcode/google/chromeos/vboot.c
+++ b/src/vendorcode/google/chromeos/vboot.c
@@ -18,6 +18,7 @@
  */
 
 #include <types.h>
+#include <console/cbmem_console.h>
 #include <console/console.h>
 #include <arch/acpi.h>
 #include <tpm.h>
diff --git a/src/vendorcode/google/chromeos/vboot_common.c b/src/vendorcode/google/chromeos/vboot_common.c
index 2e0ab2b75a..68aa31475b 100644
--- a/src/vendorcode/google/chromeos/vboot_common.c
+++ b/src/vendorcode/google/chromeos/vboot_common.c
@@ -20,6 +20,7 @@
 #include <boot/coreboot_tables.h>
 #include <cbfs.h>
 #include <cbmem.h>
+#include <console/cbmem_console.h>
 #include <console/console.h>
 #include <reset.h>
 #include <stddef.h>