soc/amd/cezanne: Force resets to be cold
Cezanne must use cold resets. Change the warm reset request to always set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power cycles, set it early for good measure. BUG=b:184281092 TEST=Majolica successfully resets using 0xcf9 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -113,8 +113,14 @@ static void fch_init_acpi_ports(void)
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PM_ACPI_TIMER_EN_EN);
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PM_ACPI_TIMER_EN_EN);
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}
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}
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static void fch_init_resets(void)
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{
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pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
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}
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void fch_init(void *chip_info)
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void fch_init(void *chip_info)
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{
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{
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fch_init_resets();
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i2c_soc_init();
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i2c_soc_init();
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fch_init_acpi_ports();
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fch_init_acpi_ports();
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@ -7,6 +7,7 @@
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/acpimmio.h>
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#include <amdblocks/reset.h>
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#include <amdblocks/reset.h>
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/* TODO: is NCP_ERR still valid? It appears reserved and always 0xff. b/184281092 */
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void set_warm_reset_flag(void)
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void set_warm_reset_flag(void)
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{
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{
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uint8_t ncp = inw(NCP_ERR);
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uint8_t ncp = inw(NCP_ERR);
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@ -29,14 +30,13 @@ void do_cold_reset(void)
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void do_warm_reset(void)
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void do_warm_reset(void)
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{
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{
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set_warm_reset_flag();
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/* Warm resets are not supported and must be executed as cold */
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pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
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/* Assert reset signals only. */
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TOGGLE_ALL_PWR_GOOD);
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outb(RST_CPU | SYS_RST, RST_CNT);
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outb(RST_CPU | SYS_RST, RST_CNT);
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}
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}
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void do_board_reset(void)
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void do_board_reset(void)
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{
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{
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/* TODO: Would a warm_reset() suffice? */
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do_cold_reset();
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do_cold_reset();
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}
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}
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