GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/cezanne: Force resets to be cold 

Cezanne must use cold resets.  Change the warm reset request to always
set TOGGLE_ALL_PWR_GOOD.  And, since the bit is sticky across power
cycles, set it early for good measure.

BUG=b:184281092
TEST=Majolica successfully resets using 0xcf9

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson 2021-05-06 16:08:09 -06:00 committed by Martin Roth
parent a204cdf75b
commit 3e1943ec46
2 changed files with 10 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/soc/amd/cezanne/fch.c
View File

@ -113,8 +113,14 @@ static void fch_init_acpi_ports(void)
PM_ACPI_TIMER_EN_EN);
}
static void fch_init_resets(void)
{
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
}
void fch_init(void *chip_info)
{
fch_init_resets();
i2c_soc_init();
fch_init_acpi_ports();

8
src/soc/amd/cezanne/reset.c
View File

@ -7,6 +7,7 @@
#include <amdblocks/acpimmio.h>
#include <amdblocks/reset.h>
/* TODO: is NCP_ERR still valid? It appears reserved and always 0xff. b/184281092 */
void set_warm_reset_flag(void)
{
uint8_t ncp = inw(NCP_ERR);
@ -29,14 +30,13 @@ void do_cold_reset(void)
void do_warm_reset(void)
{
set_warm_reset_flag();
/* Assert reset signals only. */
/* Warm resets are not supported and must be executed as cold */
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
TOGGLE_ALL_PWR_GOOD);
outb(RST_CPU | SYS_RST, RST_CNT);
}
void do_board_reset(void)
{
/* TODO: Would a warm_reset() suffice? */
do_cold_reset();
}