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soc/intel/cannonlake: Add early CPU initialization 

Add basic CPU initialization for bootblock, as well as relevant headers.

Change-Id: I318b7ea0f3aa5b5d28bf70784ccd20f2fe28cd86
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Andrey Petrov 2017-06-05 13:22:24 -07:00 committed by Aaron Durbin
parent 5b8987ae46
commit 3e2e0508c2
4 changed files with 129 additions and 0 deletions
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6
src/soc/intel/cannonlake/Kconfig
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@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select SOC_INTEL_COMMON_BLOCK_TIMER
select HAVE_MONOTONIC_TIMER
select TSC_CONSTANT_RATE
select TSC_MONOTONIC_TIMER
@ -25,6 +26,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_UART
@ -64,4 +66,8 @@ config PCR_BASE_ADDRESS
help
This option allows you to select MMIO Base Address of sideband bus.
config CPU_BCLK_MHZ
int
default 100
endif

28
src/soc/intel/cannonlake/bootblock/cpu.c Normal file
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@ -0,0 +1,28 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <intelblocks/cpulib.h>
#include <intelblocks/fast_spi.h>
#include <soc/bootblock.h>
void bootblock_cpu_init(void)
{
/* Temporarily cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED) &&
IS_ENABLED(CONFIG_BOOT_DEVICE_SPI_FLASH))
fast_spi_cache_bios_region();
}

54
src/soc/intel/cannonlake/include/soc/cpu.h Normal file
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@ -0,0 +1,54 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_CANNONLAKE_CPU_H_
#define _SOC_CANNONLAKE_CPU_H_
#include <arch/cpu.h>
#include <device/device.h>
/* Supported CPUIDs */
#define CPUID_CANNONLAKE_A0 0x60660
#define CPUID_CANNONLAKE_B0 0x60661
#define CPUID_CANNONLAKE_C0 0x60662
/* Latency times in units of 1024ns. */
#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x4e
#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x76
#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x94
#define C_STATE_LATENCY_CONTROL_3_LIMIT 0xfa
#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x14c
#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x3f2
/* Power in units of mW */
#define C1_POWER 0x3e8
#define C3_POWER 0x1f4
#define C6_POWER 0x15e
#define C7_POWER 0xc8
#define C8_POWER 0xc8
#define C9_POWER 0xc8
#define C10_POWER 0xc8
#define C_STATE_LATENCY_MICRO_SECONDS(limit, base) \
(((1 << ((base)*5)) * (limit)) / 1000)
#define C_STATE_LATENCY_FROM_LAT_REG(reg) \
C_STATE_LATENCY_MICRO_SECONDS(C_STATE_LATENCY_CONTROL_ ##reg## _LIMIT, \
(IRTL_1024_NS >> 10))
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
#endif

41
src/soc/intel/cannonlake/include/soc/msr.h Normal file
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@ -0,0 +1,41 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _SOC_MSR_H_
#define _SOC_MSR_H_
#include <intelblocks/msr.h>
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_BIOS_UPGD_TRIG 0x7a
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
#define ENERGY_POLICY_NORMAL 6
#define ENERGY_POLICY_POWERSAVE 15
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define PRMRR_PHYS_BASE_MSR 0x1f4
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define MSR_LT_LOCK_MEMORY 0x2e7
#define MSR_SGX_OWNEREPOCH0 0x300
#define MSR_SGX_OWNEREPOCH1 0x301
#define MSR_VR_CURRENT_CONFIG 0x601
#define MSR_VR_MISC_CONFIG 0x603
#define MSR_VR_MISC_CONFIG2 0x636
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP1_POWER_LIMIT 0x640
#endif