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mb/google/zork/vilboz: set the eDP phy overriden for WWAN SKU 

Move the eDP phy overridden to variant for WWAN SKU.

BUG=b:171269338
BRANCH=firmware-zork-13434.B
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I0400e8f78b152f260c632fba3cfa43aeca2f6776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Chris Wang 2021-03-30 18:32:29 +08:00 committed by Martin Roth
parent acf230c2ea
commit 3e343559e2
2 changed files with 13 additions and 14 deletions
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13
src/mainboard/google/zork/variants/vilboz/overridetree.cb
View File

@ -30,19 +30,6 @@ chip soc/amd/picasso
register "telemetry_vddcr_soc_slope_mA" = "26559"
register "telemetry_vddcr_soc_offset" = "89"
# eDP phy tuning settings
register "edp_phy_override" = "ENABLE_EDP_TUNINGSET"
# bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3
register "edp_physel" = "0x1"
register "edp_tuningset" = "{
.dp_vs_pemph_level = 0x00,
.margin_deemph = 0x004b,
.deemph_6db4 = 0x0,
.boostadj = 0x80,
}"
# eDP power sequence. all pwr sequence numbers below are in uint of 4ms,
# and "0" as default value
register "edp_pwr_adjust_enable" = "1"

14
src/mainboard/google/zork/variants/vilboz/variant.c
View File

@ -4,6 +4,7 @@
#include <soc/pci_devs.h>
#include <fw_config.h>
#include <sar.h>
#include "chip.h"
static const fsp_ddi_descriptor hdmi_ddi_descriptors[] = {
{ // DDI0, DP0, eDP
@ -40,8 +41,19 @@ void variant_devtree_update(void)
soc_cfg = config_of_soc();
/* b:/174121847 Use external OSC to mitigate noise for WWAN sku. */
if (variant_has_wwan())
if (variant_has_wwan()) {
soc_cfg->acp_i2s_use_external_48mhz_osc = 1;
/* eDP phy tuning settings */
soc_cfg->edp_phy_override = ENABLE_EDP_TUNINGSET;
/* bit vector of phy, bit0=1: DP0, bit1=1: DP1, bit2=1: DP2 bit3=1: DP3 */
soc_cfg->edp_physel = 0x1;
/* override for 0.6v 0db swing 1, pre-emphasis 0 */
soc_cfg->edp_tuningset.dp_vs_pemph_level = 0x01;
soc_cfg->edp_tuningset.margin_deemph = 0x004b;
soc_cfg->edp_tuningset.deemph_6db4 = 0x00;
soc_cfg->edp_tuningset.boostadj = 0x80;
}
}
/*