This code was copied from amdk8 and never really made usable.
It's supposed to be a userspace regression test for ram init, but in fact, it doesn't even execute ram init. This was suggested by Carl-Daniel on 2009-08-27 Thus, dropping it. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
2b962a3c39
commit
3e4a0b87c8
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@ -9,8 +9,3 @@ driver pciexp_portc.o
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default CONFIG_WRITE_HIGH_TABLES=1
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makerule raminit_test
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depends "$(TOP)/src/northbridge/intel/e7520/raminit_test.c"
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depends "$(TOP)/src/northbridge/intel/e7520/raminit.c"
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action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@"
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end
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@ -1,443 +0,0 @@
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#include <unistd.h>
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#include <limits.h>
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#include <stdint.h>
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#include <string.h>
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#include <setjmp.h>
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#include <device/pci_def.h>
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#include <stdlib.h>
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#include "e7520.h"
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jmp_buf end_buf;
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static int is_cpu_pre_c0(void)
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{
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return 0;
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}
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#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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(((FN) & 0x07) << 8) | \
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((WHERE) & 0xFF))
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#define PCI_DEV(BUS, DEV, FN) ( \
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(((BUS) & 0xFF) << 16) | \
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(((DEV) & 0x1f) << 11) | \
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(((FN) & 0x7) << 8))
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#define PCI_ID(VENDOR_ID, DEVICE_ID) \
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((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
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typedef unsigned device_t;
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unsigned char pci_register[256*5*3*256];
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static uint8_t pci_read_config8(device_t dev, unsigned where)
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{
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unsigned addr;
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addr = dev | where;
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return pci_register[addr];
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}
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static uint16_t pci_read_config16(device_t dev, unsigned where)
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{
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unsigned addr;
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addr = dev | where;
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return pci_register[addr] | (pci_register[addr + 1] << 8);
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}
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static uint32_t pci_read_config32(device_t dev, unsigned where)
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{
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unsigned addr;
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uint32_t value;
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addr = dev | where;
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value = pci_register[addr] |
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(pci_register[addr + 1] << 8) |
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(pci_register[addr + 2] << 16) |
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(pci_register[addr + 3] << 24);
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#if 0
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print_debug("pcir32(");
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print_debug_hex32(addr);
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print_debug("):");
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print_debug_hex32(value);
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print_debug("\n");
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#endif
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return value;
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}
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static void pci_write_config8(device_t dev, unsigned where, uint8_t value)
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{
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unsigned addr;
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addr = dev | where;
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pci_register[addr] = value;
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}
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static void pci_write_config16(device_t dev, unsigned where, uint16_t value)
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{
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unsigned addr;
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addr = dev | where;
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pci_register[addr] = value & 0xff;
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pci_register[addr + 1] = (value >> 8) & 0xff;
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}
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static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
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{
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unsigned addr;
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addr = dev | where;
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pci_register[addr] = value & 0xff;
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pci_register[addr + 1] = (value >> 8) & 0xff;
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pci_register[addr + 2] = (value >> 16) & 0xff;
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pci_register[addr + 3] = (value >> 24) & 0xff;
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#if 0
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print_debug("pciw32(");
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print_debug_hex32(addr);
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print_debug(", ");
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print_debug_hex32(value);
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print_debug(")\n");
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#endif
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}
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#define PCI_DEV_INVALID (0xffffffffU)
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static device_t pci_locate_device(unsigned pci_id, device_t dev)
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{
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for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
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unsigned int id;
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id = pci_read_config32(dev, 0);
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if (id == pci_id) {
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return dev;
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}
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}
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return PCI_DEV_INVALID;
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}
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static void uart_tx_byte(unsigned char data)
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{
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write(STDOUT_FILENO, &data, 1);
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}
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static void hlt(void)
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{
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longjmp(end_buf, 2);
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}
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#include "../../../arch/i386/lib/console.c"
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unsigned long log2(unsigned long x)
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{
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// assume 8 bits per byte.
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unsigned long i = 1 << (sizeof(x)*8 - 1);
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unsigned long pow = sizeof(x) * 8 - 1;
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if (! x) {
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static const char errmsg[] = " called with invalid parameter of 0\n";
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write(STDERR_FILENO, __func__, sizeof(__func__) - 1);
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write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1);
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hlt();
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}
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for(; i > x; i >>= 1, pow--)
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;
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return pow;
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}
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typedef struct msr_struct
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{
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unsigned lo;
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unsigned hi;
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} msr_t;
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static inline msr_t rdmsr(unsigned index)
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{
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msr_t result;
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result.lo = 0;
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result.hi = 0;
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return result;
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}
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static inline void wrmsr(unsigned index, msr_t msr)
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{
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}
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#include "raminit.h"
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#define SIO_BASE 0x2e
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static void hard_reset(void)
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{
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/* FIXME implement the hard reset case... */
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longjmp(end_buf, 3);
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}
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static void memreset_setup(void)
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{
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/* Nothing to do */
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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/* Nothing to do */
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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static uint8_t spd_mt4lsdt464a[256] =
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{
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0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70,
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0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01,
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0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F,
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0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E,
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0x9C, 0xE4, 0xB7, 0x46, 0x2C, 0xFF, 0x01, 0x02, 0x03, 0x04,
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0x05, 0x06, 0x07, 0x08, 0x09, 0x01, 0x02, 0x03, 0x04, 0x05,
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0x06, 0x07, 0x08, 0x09, 0x00,
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};
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static uint8_t spd_micron_512MB_DDR333[256] =
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{
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0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60,
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0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
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0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
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0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31,
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0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43,
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0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff
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};
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static uint8_t spd_micron_256MB_DDR333[256] =
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{
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0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60,
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0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
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0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
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0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36,
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0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31,
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0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
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};
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#define MAX_DIMMS 16
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static uint8_t spd_data[MAX_DIMMS*256];
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static unsigned spd_count, spd_fail_count;
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static int spd_read_byte(unsigned device, unsigned address)
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{
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int result;
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spd_count++;
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if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) {
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result = -1;
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}
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else {
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device -= 0x50;
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if (address > 256) {
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result = -1;
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}
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else if (spd_data[(device << 8) | 2] != 7) {
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result = -1;
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}
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else {
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result = spd_data[(device << 8) | address];
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}
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}
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#if 0
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print_debug("spd_read_byte(");
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print_debug_hex32(device);
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print_debug(", ");
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print_debug_hex32(address);
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print_debug(") -> ");
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print_debug_hex32(result);
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print_debug("\n");
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#endif
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if (spd_count >= spd_fail_count) {
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result = -1;
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}
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return result;
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}
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/* no specific code here. this should go away completely */
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static void coherent_ht_mainboard(unsigned cpus)
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{
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}
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#include "raminit.c"
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#include "../../../lib/generic_sdram.c"
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#define FIRST_CPU 1
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#define SECOND_CPU 1
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
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static void raminit_main(void)
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{
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/*
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* GPIO28 of 8111 will control H0_MEMRESET_L
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* GPIO29 of 8111 will control H1_MEMRESET_L
|
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*/
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static const struct mem_controller cpu[] = {
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#if FIRST_CPU
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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.f1 = PCI_DEV(0, 0x18, 1),
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.f2 = PCI_DEV(0, 0x18, 2),
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.f3 = PCI_DEV(0, 0x18, 3),
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.channel0 = { 0x50+0, 0x50+2, 0x50+4, 0x50+6 },
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.channel1 = { 0x50+1, 0x50+3, 0x50+5, 0x50+7 },
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},
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#endif
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#if SECOND_CPU
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{
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.node_id = 1,
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { 0x50+8, 0x50+10, 0x50+12, 0x50+14 },
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.channel1 = { 0x50+9, 0x50+11, 0x50+13, 0x50+15 },
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},
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#endif
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};
|
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console_init();
|
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memreset_setup();
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sdram_initialize(ARRAY_SIZE(cpu), cpu);
|
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|
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}
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|
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static void reset_tests(void)
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{
|
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/* Clear the results of any previous tests */
|
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memset(pci_register, 0, sizeof(pci_register));
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memset(spd_data, 0, sizeof(spd_data));
|
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spd_count = 0;
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spd_fail_count = UINT_MAX;
|
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|
||||
pci_write_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP,
|
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NBCAP_128Bit |
|
||||
NBCAP_MP| NBCAP_BIG_MP |
|
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/* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
|
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(NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
|
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NBCAP_MEMCTRL);
|
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|
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pci_write_config32(PCI_DEV(0, 0x19, 3), NORTHBRIDGE_CAP,
|
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NBCAP_128Bit |
|
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NBCAP_MP| NBCAP_BIG_MP |
|
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/* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
|
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(NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
|
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NBCAP_MEMCTRL);
|
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|
||||
#if 0
|
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pci_read_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP);
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#endif
|
||||
}
|
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|
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static void test1(void)
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{
|
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reset_tests();
|
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|
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memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
|
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memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
|
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#if 0
|
||||
memcpy(&spd_data[2*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[3*256], spd_micron_512MB_DDR333, 256);
|
||||
|
||||
memcpy(&spd_data[8*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[9*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[10*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[11*256], spd_micron_512MB_DDR333, 256);
|
||||
#endif
|
||||
|
||||
raminit_main();
|
||||
|
||||
#if 0
|
||||
print_debug("spd_count: ");
|
||||
print_debug_hex32(spd_count);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
|
||||
static void do_test2(int i)
|
||||
{
|
||||
jmp_buf tmp_buf;
|
||||
memcpy(&tmp_buf, &end_buf, sizeof(end_buf));
|
||||
if (setjmp(end_buf) != 0) {
|
||||
goto done;
|
||||
}
|
||||
reset_tests();
|
||||
spd_fail_count = i;
|
||||
|
||||
print_debug("\r\nSPD will fail after: ");
|
||||
print_debug_hex32(spd_fail_count);
|
||||
print_debug(" accesses.\r\n");
|
||||
|
||||
memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
|
||||
|
||||
raminit_main();
|
||||
|
||||
done:
|
||||
memcpy(&end_buf, &tmp_buf, sizeof(end_buf));
|
||||
}
|
||||
|
||||
static void test2(void)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < 0x48; i++) {
|
||||
do_test2(i);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
if (setjmp(end_buf) != 0) {
|
||||
return -1;
|
||||
}
|
||||
test1();
|
||||
test2();
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -9,8 +9,3 @@ driver pciexp_portc.o
|
|||
|
||||
default CONFIG_WRITE_HIGH_TABLES=1
|
||||
|
||||
makerule raminit_test
|
||||
depends "$(TOP)/src/northbridge/intel/e7525/raminit_test.c"
|
||||
depends "$(TOP)/src/northbridge/intel/e7525/raminit.c"
|
||||
action "$(HOSTCC) $(HOSTCFLAGS) $(CPUFLAGS) -Wno-unused-function -I$(TOP)/src/include -g $< -o $@"
|
||||
end
|
||||
|
|
|
|||
|
|
@ -1,394 +0,0 @@
|
|||
#include <unistd.h>
|
||||
#include <limits.h>
|
||||
#include <stdint.h>
|
||||
#include <string.h>
|
||||
#include <setjmp.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <stdlib.h>
|
||||
#include "e7525.h"
|
||||
|
||||
jmp_buf end_buf;
|
||||
|
||||
static int is_cpu_pre_c0(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
|
||||
(((BUS) & 0xFF) << 16) | \
|
||||
(((DEV) & 0x1f) << 11) | \
|
||||
(((FN) & 0x07) << 8) | \
|
||||
((WHERE) & 0xFF))
|
||||
|
||||
#define PCI_DEV(BUS, DEV, FN) ( \
|
||||
(((BUS) & 0xFF) << 16) | \
|
||||
(((DEV) & 0x1f) << 11) | \
|
||||
(((FN) & 0x7) << 8))
|
||||
|
||||
#define PCI_ID(VENDOR_ID, DEVICE_ID) \
|
||||
((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
|
||||
|
||||
typedef unsigned device_t;
|
||||
|
||||
unsigned char pci_register[256*5*3*256];
|
||||
|
||||
static uint8_t pci_read_config8(device_t dev, unsigned where)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
return pci_register[addr];
|
||||
}
|
||||
|
||||
static uint16_t pci_read_config16(device_t dev, unsigned where)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
return pci_register[addr] | (pci_register[addr + 1] << 8);
|
||||
}
|
||||
|
||||
static uint32_t pci_read_config32(device_t dev, unsigned where)
|
||||
{
|
||||
unsigned addr;
|
||||
uint32_t value;
|
||||
addr = dev | where;
|
||||
value = pci_register[addr] |
|
||||
(pci_register[addr + 1] << 8) |
|
||||
(pci_register[addr + 2] << 16) |
|
||||
(pci_register[addr + 3] << 24);
|
||||
|
||||
return value;
|
||||
|
||||
}
|
||||
|
||||
static void pci_write_config8(device_t dev, unsigned where, uint8_t value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
pci_register[addr] = value;
|
||||
}
|
||||
|
||||
static void pci_write_config16(device_t dev, unsigned where, uint16_t value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
pci_register[addr] = value & 0xff;
|
||||
pci_register[addr + 1] = (value >> 8) & 0xff;
|
||||
}
|
||||
|
||||
static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
pci_register[addr] = value & 0xff;
|
||||
pci_register[addr + 1] = (value >> 8) & 0xff;
|
||||
pci_register[addr + 2] = (value >> 16) & 0xff;
|
||||
pci_register[addr + 3] = (value >> 24) & 0xff;
|
||||
}
|
||||
|
||||
#define PCI_DEV_INVALID (0xffffffffU)
|
||||
static device_t pci_locate_device(unsigned pci_id, device_t dev)
|
||||
{
|
||||
for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
|
||||
unsigned int id;
|
||||
id = pci_read_config32(dev, 0);
|
||||
if (id == pci_id) {
|
||||
return dev;
|
||||
}
|
||||
}
|
||||
return PCI_DEV_INVALID;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
static void uart_tx_byte(unsigned char data)
|
||||
{
|
||||
write(STDOUT_FILENO, &data, 1);
|
||||
}
|
||||
static void hlt(void)
|
||||
{
|
||||
longjmp(end_buf, 2);
|
||||
}
|
||||
#include "../../../arch/i386/lib/console.c"
|
||||
|
||||
unsigned long log2(unsigned long x)
|
||||
{
|
||||
// assume 8 bits per byte.
|
||||
unsigned long i = 1 << (sizeof(x)*8 - 1);
|
||||
unsigned long pow = sizeof(x) * 8 - 1;
|
||||
|
||||
if (! x) {
|
||||
static const char errmsg[] = " called with invalid parameter of 0\n";
|
||||
write(STDERR_FILENO, __func__, sizeof(__func__) - 1);
|
||||
write(STDERR_FILENO, errmsg, sizeof(errmsg) - 1);
|
||||
hlt();
|
||||
}
|
||||
for(; i > x; i >>= 1, pow--)
|
||||
;
|
||||
|
||||
return pow;
|
||||
}
|
||||
|
||||
typedef struct msr_struct
|
||||
{
|
||||
unsigned lo;
|
||||
unsigned hi;
|
||||
} msr_t;
|
||||
|
||||
static inline msr_t rdmsr(unsigned index)
|
||||
{
|
||||
msr_t result;
|
||||
result.lo = 0;
|
||||
result.hi = 0;
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline void wrmsr(unsigned index, msr_t msr)
|
||||
{
|
||||
}
|
||||
|
||||
#include "raminit.h"
|
||||
|
||||
#define SIO_BASE 0x2e
|
||||
|
||||
static void hard_reset(void)
|
||||
{
|
||||
/* FIXME implement the hard reset case... */
|
||||
longjmp(end_buf, 3);
|
||||
}
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
/* Nothing to do */
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
|
||||
static uint8_t spd_mt4lsdt464a[256] =
|
||||
{
|
||||
0x80, 0x08, 0x04, 0x0C, 0x08, 0x01, 0x40, 0x00, 0x01, 0x70,
|
||||
0x54, 0x00, 0x80, 0x10, 0x00, 0x01, 0x8F, 0x04, 0x06, 0x01,
|
||||
0x01, 0x00, 0x0E, 0x75, 0x54, 0x00, 0x00, 0x0F, 0x0E, 0x0F,
|
||||
|
||||
0x25, 0x08, 0x15, 0x08, 0x15, 0x08, 0x00, 0x12, 0x01, 0x4E,
|
||||
0x9C, 0xE4, 0xB7, 0x46, 0x2C, 0xFF, 0x01, 0x02, 0x03, 0x04,
|
||||
0x05, 0x06, 0x07, 0x08, 0x09, 0x01, 0x02, 0x03, 0x04, 0x05,
|
||||
0x06, 0x07, 0x08, 0x09, 0x00,
|
||||
};
|
||||
|
||||
static uint8_t spd_micron_512MB_DDR333[256] =
|
||||
{
|
||||
0x80, 0x08, 0x07, 0x0d, 0x0b, 0x02, 0x48, 0x00, 0x04, 0x60,
|
||||
0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
|
||||
0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
|
||||
0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x3c, 0x48, 0x30, 0x28, 0x50, 0x00, 0x01, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x10, 0x6f, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0x01, 0x33, 0x36, 0x56, 0x44, 0x44, 0x46, 0x31,
|
||||
0x32, 0x38, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43,
|
||||
0x33, 0x03, 0x00, 0x03, 0x23, 0x17, 0x07, 0x5a, 0xb2, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff
|
||||
};
|
||||
|
||||
static uint8_t spd_micron_256MB_DDR333[256] =
|
||||
{
|
||||
0x80, 0x08, 0x07, 0x0d, 0x0b, 0x01, 0x48, 0x00, 0x04, 0x60,
|
||||
0x70, 0x02, 0x82, 0x04, 0x04, 0x01, 0x0e, 0x04, 0x0c, 0x01,
|
||||
0x02, 0x26, 0xc0, 0x75, 0x70, 0x00, 0x00, 0x48, 0x30, 0x48,
|
||||
0x2a, 0x80, 0x80, 0x80, 0x45, 0x45, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x3c, 0x48, 0x30, 0x23, 0x50, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x58, 0x2c, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0x01, 0x31, 0x38, 0x56, 0x44, 0x44, 0x46, 0x36,
|
||||
0x34, 0x37, 0x32, 0x47, 0x2d, 0x33, 0x33, 0x35, 0x43, 0x31,
|
||||
0x20, 0x01, 0x00, 0x03, 0x19, 0x17, 0x05, 0xb2, 0xf4, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
|
||||
};
|
||||
|
||||
#define MAX_DIMMS 16
|
||||
static uint8_t spd_data[MAX_DIMMS*256];
|
||||
|
||||
static unsigned spd_count, spd_fail_count;
|
||||
static int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
int result;
|
||||
spd_count++;
|
||||
if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) {
|
||||
result = -1;
|
||||
}
|
||||
else {
|
||||
device -= 0x50;
|
||||
|
||||
if (address > 256) {
|
||||
result = -1;
|
||||
}
|
||||
else if (spd_data[(device << 8) | 2] != 7) {
|
||||
result = -1;
|
||||
}
|
||||
else {
|
||||
result = spd_data[(device << 8) | address];
|
||||
}
|
||||
}
|
||||
if (spd_count >= spd_fail_count) {
|
||||
result = -1;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
#include "raminit.c"
|
||||
#include "../../../lib/generic_sdram.c"
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 1
|
||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
#if 0
|
||||
static void raminit_main(void)
|
||||
{
|
||||
/*
|
||||
* GPIO28 of 8111 will control H0_MEMRESET_L
|
||||
* GPIO29 of 8111 will control H1_MEMRESET_L
|
||||
*/
|
||||
static const struct mem_controller cpu[] = {
|
||||
#if FIRST_CPU
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x18, 0),
|
||||
.f1 = PCI_DEV(0, 0x18, 1),
|
||||
.f2 = PCI_DEV(0, 0x18, 2),
|
||||
.f3 = PCI_DEV(0, 0x18, 3),
|
||||
.channel0 = { 0x50+0, 0x50+2, 0x50+4, 0x50+6 },
|
||||
.channel1 = { 0x50+1, 0x50+3, 0x50+5, 0x50+7 },
|
||||
},
|
||||
#endif
|
||||
#if SECOND_CPU
|
||||
{
|
||||
.node_id = 1,
|
||||
.f0 = PCI_DEV(0, 0x19, 0),
|
||||
.f1 = PCI_DEV(0, 0x19, 1),
|
||||
.f2 = PCI_DEV(0, 0x19, 2),
|
||||
.f3 = PCI_DEV(0, 0x19, 3),
|
||||
.channel0 = { 0x50+8, 0x50+10, 0x50+12, 0x50+14 },
|
||||
.channel1 = { 0x50+9, 0x50+11, 0x50+13, 0x50+15 },
|
||||
},
|
||||
#endif
|
||||
};
|
||||
console_init();
|
||||
memreset_setup();
|
||||
sdram_initialize(ARRAY_SIZE(cpu), cpu);
|
||||
|
||||
}
|
||||
#endif
|
||||
static void reset_tests(void)
|
||||
{
|
||||
/* Clear the results of any previous tests */
|
||||
memset(pci_register, 0, sizeof(pci_register));
|
||||
memset(spd_data, 0, sizeof(spd_data));
|
||||
spd_count = 0;
|
||||
spd_fail_count = UINT_MAX;
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x18, 3), NORTHBRIDGE_CAP,
|
||||
NBCAP_128Bit |
|
||||
NBCAP_MP| NBCAP_BIG_MP |
|
||||
/* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
|
||||
(NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
|
||||
NBCAP_MEMCTRL);
|
||||
|
||||
pci_write_config32(PCI_DEV(0, 0x19, 3), NORTHBRIDGE_CAP,
|
||||
NBCAP_128Bit |
|
||||
NBCAP_MP| NBCAP_BIG_MP |
|
||||
/* NBCAP_ECC | NBCAP_CHIPKILL_ECC | */
|
||||
(NBCAP_MEMCLK_200MHZ << NBCAP_MEMCLK_SHIFT) |
|
||||
NBCAP_MEMCTRL);
|
||||
}
|
||||
|
||||
static void test1(void)
|
||||
{
|
||||
reset_tests();
|
||||
|
||||
memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
|
||||
// raminit_main();
|
||||
}
|
||||
|
||||
|
||||
static void do_test2(int i)
|
||||
{
|
||||
jmp_buf tmp_buf;
|
||||
memcpy(&tmp_buf, &end_buf, sizeof(end_buf));
|
||||
if (setjmp(end_buf) != 0) {
|
||||
goto done;
|
||||
}
|
||||
reset_tests();
|
||||
spd_fail_count = i;
|
||||
|
||||
print_debug("\r\nSPD will fail after: ");
|
||||
print_debug_hex32(spd_fail_count);
|
||||
print_debug(" accesses.\r\n");
|
||||
|
||||
memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
|
||||
memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
|
||||
|
||||
// raminit_main();
|
||||
|
||||
done:
|
||||
memcpy(&end_buf, &tmp_buf, sizeof(end_buf));
|
||||
}
|
||||
|
||||
static void test2(void)
|
||||
{
|
||||
int i;
|
||||
for(i = 0; i < 0x48; i++) {
|
||||
do_test2(i);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
int main(int argc, char **argv)
|
||||
{
|
||||
if (setjmp(end_buf) != 0) {
|
||||
return -1;
|
||||
}
|
||||
test1();
|
||||
test2();
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue