mainboard: add Supermicro X9SCL/X9SCM
Boots to Linux. Works: - CPU (Core i3-2120 tested) - Memory (one 1GB 1Rx8 PC3-10600E module tested) - Slots 4, 6, 7 To fix/improve: - SuperIO hardware monitor setup for PECI and fan control - SuperIO ASL in DSDT (e.g. UART Devices) - PEG PCIe lanes (should show x8 max width instead of x16 on 0:1.0 for Slot 7) Untested: - IPMI where BMC is fully implemented (X9SC[LM](+)-F variants) - GbE on X9SCL+-F (where there are two 82574L instead of one) - Slot 5 (x4 on 0:06.0) (only applicable to X9SCM variants) Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Change-Id: I985db89d67de21bbafbdc34d7044496434a6eb17 Depends-On: I5b7599746195cfa996a48320404a8dbe6820483a, I1206746332c9939a78b67e7b48d3098bdef8a2ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/38346 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jonathan A. Kollasch
Patrick Georgi
parent
dd662870dd
commit
3e4f7a39f8
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@ -0,0 +1,55 @@
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if BOARD_SUPERMICRO_X9SCL
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_8192
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select HAVE_ACPI_TABLES
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select NORTHBRIDGE_INTEL_SANDYBRIDGE
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select USE_NATIVE_RAMINIT
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select RAMINIT_ENABLE_ECC
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select SERIRQ_CONTINUOUS_MODE
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select SOUTHBRIDGE_INTEL_BD82X6X
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select SUPERIO_NUVOTON_NCT6776
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select SUPERIO_NUVOTON_NCT6776_COM_A
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select SUPERIO_NUVOTON_WPCM450
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select MAINBOARD_USES_IFD_GBE_REGION
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config MAINBOARD_DIR
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string
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default supermicro/x9scl
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config MAINBOARD_PART_NUMBER
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string
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default "X9SCL/X9SCM"
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX
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int
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default 1
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config VGA_BIOS_FILE
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string
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default "pci102b,0532.rom"
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config VGA_BIOS_ID
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string
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depends on VGA_BIOS
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default "102b,0532"
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config PXE_ROM_ID
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string
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depends on PXE
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default "8086:10d3"
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config CBFS_SIZE
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hex
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default 0x400000
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#config SUPERMICRO_BOARDID
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# string
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# default "0624"
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#
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endif
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@ -0,0 +1,2 @@
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config BOARD_SUPERMICRO_X9SCL
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bool "X9SCL/X9SCM"
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@ -0,0 +1,4 @@
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bootblock-y += early_init.c
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bootblock-y += gpio.c
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romstage-y += early_init.c
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romstage-y += gpio.c
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@ -0,0 +1,11 @@
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* This file is part of the coreboot project. */
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Method(_WAK, 1)
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{
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Return (Package() { 0, 0 })
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}
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Method(_PTS, 1)
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{
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}
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* This file is part of the coreboot project. */
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#define SUPERIO_DEV SIO0
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#define SUPERIO_PNP_BASE 0x2e
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#undef NCT6776_SHOW_PP
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#define NCT6776_SHOW_SP1
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#define NCT6776_SHOW_KBC
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#undef NCT6776_SHOW_GPIO
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#define NCT6776_SHOW_HWM
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#include <superio/nuvoton/nct6776/acpi/superio.asl>
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@ -0,0 +1,10 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#include <southbridge/intel/bd82x6x/nvs.h>
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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gnvs->tcrt = 100;
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gnvs->tpsv = 90;
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}
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@ -0,0 +1,7 @@
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Category: server
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Board URL:
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ROM package: SOIC-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2011
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@ -0,0 +1,127 @@
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chip northbridge/intel/sandybridge
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device cpu_cluster 0 on
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chip cpu/intel/model_206ax # FIXME: check all registers
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register "c1_acpower" = "1"
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register "c1_battery" = "1"
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register "c2_acpower" = "3"
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register "c2_battery" = "3"
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register "c3_acpower" = "5"
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register "c3_battery" = "5"
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device lapic 0x0 on end
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device lapic 0xacac off end
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end
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end
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device domain 0 on
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subsystemid 0x15d9 0x0624 inherit
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device pci 00.0 on end # Host bridge
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device pci 01.0 on end # PEG
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device pci 01.1 on end # PEG
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device pci 02.0 off end # iGPU
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device pci 06.0 on end # PEG
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chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
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register "c2_latency" = "0x0065"
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register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff)
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register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff)
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register "gen3_dec" = "0x00040ca1" # IPMI KCS (0x0ca0-0ca3)
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register "gen4_dec" = "0x001c03e1" # 3rd UART (0x03e0-03ff)
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register "pcie_port_coalesce" = "1"
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register "sata_interface_speed_support" = "0x3"
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register "sata_port_map" = "0x3f"
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register "spi_lvscc" = "0x2005"
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register "spi_uvscc" = "0x2005"
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device pci 16.0 off end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 19.0 on # Intel Gigabit Ethernet (not for X9SCL+-F)
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subsystemid 0x15d9 0x1502
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end
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device pci 1a.0 on end # USB2 EHCI #2
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device pci 1b.0 off end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 on # PCIe Port #5
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device pci 00.0 on end # primary 574 GigE
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end
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device pci 1c.5 off end # PCIe Port #6
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device pci 1c.6 on # PCIe Port #7
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device pci 00.0 on end # secondary 574 GigE on X9SCL+-F
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end
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device pci 1c.7 off end # PCIe Port #8
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device pci 1d.0 on end # USB2 EHCI #1
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device pci 1e.0 on # PCI bridge
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device pci 03.0 on end # Matrox G200e in BMC
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end
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device pci 1f.0 on # LPC bridge
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chip superio/nuvoton/nct6776
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device pnp 2e.0 off end # Floppy
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device pnp 2e.1 off end # Parallel port
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device pnp 2e.2 on # COM1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.3 on # COM2, IR
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.5 on # Keyboard
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io 0x60 = 0x060
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io 0x62 = 0x064
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irq 0x70 = 1
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irq 0x72 = 12
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end
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device pnp 2e.6 off end # CIR
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device pnp 2e.7 off end # GPIO6
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device pnp 2e.107 off end # GPIO7
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device pnp 2e.207 off end # GPIO8
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device pnp 2e.307 off end # GPIO9
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device pnp 2e.8 off end # WDT
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device pnp 2e.108 on end # GPIO0
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device pnp 2e.208 off end # GPIOA
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device pnp 2e.308 on # GPIOBASE
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io 0x60 = 0xa80
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end
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device pnp 2e.109 off end # GPIO1
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device pnp 2e.209 on # GPIO2
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end
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device pnp 2e.309 on # GPIO3
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end
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device pnp 2e.409 off end # GPIO4
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device pnp 2e.509 off end # GPIO5
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device pnp 2e.609 off end # GPIO6
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device pnp 2e.709 off end # GPIO7
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device pnp 2e.a off end # ACPI
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device pnp 2e.b on # HWM, front panel LED
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io 0x60 = 0xa30
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io 0x62 = 0
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end
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device pnp 2e.d off end # VID
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device pnp 2e.e off end # CIR WAKE-UP
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device pnp 2e.f off end # GPIO
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device pnp 2e.14 off end # SVID
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device pnp 2e.16 off end # Deep sleep
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device pnp 2e.17 off end # GPIOA
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end
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chip drivers/ipmi
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register "wait_for_bmc" = "1"
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register "bmc_boot_timeout" = "60"
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device pnp ca2.0 off end # IPMI KCS
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end
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chip superio/nuvoton/wpcm450
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device pnp 164e.2 on
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io 0x60 = 0x03e8
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irq 0x70 = 10
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end
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device pnp 164e.3 off end
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device pnp 164e.6 off end
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end
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end
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device pci 1f.2 on end # SATA Controller 1
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device pci 1f.3 on end # SMBus
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device pci 1f.5 off end # SATA Controller 2
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device pci 1f.6 off end # Thermal
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end
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end
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end
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/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* This file is part of the coreboot project. */
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#include <arch/acpi.h>
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DefinitionBlock(
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"dsdt.aml",
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"DSDT",
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0x02, /* DSDT Revision: ACPI v2.0 and up */
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OEM_ID,
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ACPI_TABLE_CREATOR,
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0x20171231 /* OEM Revision */
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)
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{
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#include "acpi/platform.asl"
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#include <cpu/intel/common/acpi/cpu.asl>
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#include <southbridge/intel/common/acpi/platform.asl>
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#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
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#include <southbridge/intel/common/acpi/sleepstates.asl>
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Device (\_SB.PCI0)
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{
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#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
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#include <southbridge/intel/bd82x6x/acpi/pch.asl>
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Device (PCIB)
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{
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Name (_ADR, 0x001E0000)
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Name (_PRW, Package(){ 13, 4 })
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Method (_PRT)
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{
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If (PICM) {
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Return (Package() {
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Package() { 0x0003ffff, 0, 0, 0x17 },
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})
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}
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Return (Package() {
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Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
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})
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}
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}
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}
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Scope (\_SB.PCI0.PEGP.DEV0)
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{
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Name (_SUN, 7)
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}
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Scope (\_SB.PCI0.PEG1.DEV0)
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{
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Name (_SUN, 6)
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}
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Scope (\_SB.PCI0.PEG6.DEV0)
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{
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Name (_SUN, 5)
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}
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Scope (\_SB.PCI0.RP01)
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{
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Device (DEV0)
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{
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Name (_ADR, 0x00000000)
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Name (_SUN, 4)
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}
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}
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}
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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/* FIXME: Check if all includes are needed. */
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#include <stdint.h>
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#include <string.h>
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#include <timestamp.h>
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#include <arch/byteorder.h>
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#include <device/mmio.h>
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#include <device/pci_ops.h>
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#include <device/pnp_def.h>
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#include <device/pnp_ops.h>
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#include <console/console.h>
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#include <bootblock_common.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <southbridge/intel/common/gpio.h>
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#include <superio/nuvoton/common/nuvoton.h>
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#include <superio/nuvoton/nct6776/nct6776.h>
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#include <superio/nuvoton/wpcm450/wpcm450.h>
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#include "x9scl.h"
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#define SERIAL_DEV PNP_DEV(X9SCL_NCT6776_PNP_BASE, NCT6776_SP1)
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#define KCS_DEV PNP_DEV(X9SCL_WPCM450_PNP_BASE, 0x11)
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#define SUPERIO_INITVAL(reg, data) {(reg), (data)}
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#define SUPERIO_BANK(x) SUPERIO_INITVAL(0x07, (x))
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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{ 1, 0, 0 }, /* ? USB0 1d.0 port 1 */
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{ 1, 0, 0 }, /* ? USB1 1d.0 port 2 */
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{ 1, 0, 1 }, /* ? USB2 1d.0 port 3 */
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{ 1, 0, 1 }, /* ? USB3 1d.0 port 4 */
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{ 1, 0, 2 }, /* ? USB4 1d.0 port 5 */
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{ 1, 0, 2 }, /* ? USB5 1d.0 port 6 */
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{ 1, 0, 3 }, /* ? ??? 1a.0 port 1 */
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{ 1, 0, 3 }, /* ? BMC 1a.0 port 2 */
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{ 1, 0, 4 }, /* ? ??? 1a.0 port 3 */
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{ 1, 0, 4 }, /* ? USB11 1a.0 port 4 */
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{ 1, 0, 6 }, /* ? USB12 1a.0 port 5 */
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{ 1, 0, 5 }, /* ? USB13 1a.0 port 6 */
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{ 1, 0, 5 },
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{ 1, 0, 6 },
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};
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static const uint8_t superio_initvals[][2] = {
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/* Global config registers */
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SUPERIO_INITVAL(0x1a, 0xc8),
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SUPERIO_INITVAL(0x1b, 0x68),
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SUPERIO_INITVAL(0x1c, 0x83),
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SUPERIO_INITVAL(0x24, 0x24),
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//SUPERIO_INITVAL(0x27, 0x00),
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SUPERIO_INITVAL(0x2a, 0x00),
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SUPERIO_INITVAL(0x2b, 0x42),
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SUPERIO_INITVAL(0x2c, 0x80),
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SUPERIO_BANK(0x9), /* GPIO[2345] */
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SUPERIO_INITVAL(0x30, 0x0c),
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SUPERIO_INITVAL(0xe0, 0xcf),
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SUPERIO_INITVAL(0xe4, 0xbd),
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SUPERIO_INITVAL(0xe5, 0x42),
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SUPERIO_INITVAL(0xe9, 0x10),
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SUPERIO_INITVAL(0xea, 0x40),
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SUPERIO_INITVAL(0xf0, 0xff),
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SUPERIO_INITVAL(0xf1, 0x02),
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SUPERIO_BANK(0xb), /* HWM & LED */
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SUPERIO_INITVAL(0xf7, 0x07),
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SUPERIO_INITVAL(0xf8, 0x40),
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SUPERIO_INITVAL(0x30, 0x01),
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SUPERIO_INITVAL(0x60, X9SCL_NCT6776_HWM_BASE >> 8),
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SUPERIO_INITVAL(0x61, X9SCL_NCT6776_HWM_BASE & 0xff),
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SUPERIO_BANK(0x5), /* KBC */
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SUPERIO_INITVAL(0xf0, 0x83),
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SUPERIO_INITVAL(0x30, 0x01),
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SUPERIO_BANK(0x0), /* FDC */
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SUPERIO_INITVAL(0x30, 0x80),
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#if 0
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SUPERIO_BANK(8),
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SUPERIO_INITVAL(0x30, 0x0a),
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SUPERIO_INITVAL(0x60, X9SCL_NCT6776_GPIO_BASE >> 8),
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SUPERIO_INITVAL(0x61, X9SCL_NCT6776_GPIO_BASE & 0xff),
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SUPERIO_INITVAL(0xe1, 0xf9),
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SUPERIO_BANK(0xa),
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SUPERIO_INITVAL(0xe4, 0x60),
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#endif
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};
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static void superio_init(void)
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{
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const pnp_devfn_t dev = PNP_DEV(X9SCL_NCT6776_PNP_BASE, 0);
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nuvoton_pnp_enter_conf_state(dev);
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for (size_t i = 0; i < ARRAY_SIZE(superio_initvals); i++)
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pnp_write_config(dev, superio_initvals[i][0], superio_initvals[i][1]);
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nuvoton_pnp_exit_conf_state(dev);
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}
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static void bmc_init(void)
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{
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pnp_devfn_t dev = KCS_DEV;
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pnp_write_config(dev, 0x21, 0x11);
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pnp_set_logical_device(dev);
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pnp_set_enable(dev, 0);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, X9SCL_WPCM450_KCS_BASE + 0);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO1, X9SCL_WPCM450_KCS_BASE + 1);
|
||||
pnp_set_iobase(dev, PNP_IDX_IRQ0, 0);
|
||||
pnp_set_enable(dev, 1);
|
||||
|
||||
#if 0
|
||||
//wpcm450_enable_dev(WPCM450_SP2, X9SCL_WPCM450_PNP_BASE, 0x03e8);
|
||||
//wpcm450_enable_dev(WPCM450_SP1, X9SCL_WPCM450_PNP_BASE, 0x02e8);
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP2);
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 0);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, 0x03e8);
|
||||
pnp_set_enable(dev, 1);
|
||||
|
||||
dev = PNP_DEV(X9SCL_WPCM450_PNP_BASE, WPCM450_SP1);
|
||||
pnp_set_logical_device(dev);
|
||||
pnp_set_enable(dev, 0);
|
||||
pnp_set_iobase(dev, PNP_IDX_IO0, 0x02e8);
|
||||
pnp_set_enable(dev, 0);
|
||||
#endif
|
||||
}
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
superio_init();
|
||||
bmc_init();
|
||||
}
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
{
|
||||
read_spd(&spd[0], 0x50, id_only);
|
||||
read_spd(&spd[1], 0x51, id_only);
|
||||
read_spd(&spd[2], 0x52, id_only);
|
||||
read_spd(&spd[3], 0x53, id_only);
|
||||
}
|
||||
|
||||
void mainboard_early_init(int s3resume)
|
||||
{
|
||||
/* Disable IGD VGA decode, no GTT or GFX stolen */
|
||||
pci_write_config16(PCI_DEV(0, 0, 0), GGC, 2);
|
||||
}
|
||||
|
|
@ -0,0 +1,183 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* This file is part of the coreboot project. */
|
||||
|
||||
#include <southbridge/intel/common/gpio.h>
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO,
|
||||
.gpio2 = GPIO_MODE_NATIVE,
|
||||
.gpio3 = GPIO_MODE_NATIVE,
|
||||
.gpio4 = GPIO_MODE_NATIVE,
|
||||
.gpio5 = GPIO_MODE_NATIVE,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_NATIVE,
|
||||
.gpio10 = GPIO_MODE_NATIVE,
|
||||
.gpio11 = GPIO_MODE_GPIO,
|
||||
.gpio12 = GPIO_MODE_NATIVE,
|
||||
.gpio13 = GPIO_MODE_GPIO,
|
||||
.gpio14 = GPIO_MODE_GPIO,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_GPIO,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_NATIVE,
|
||||
.gpio19 = GPIO_MODE_NATIVE,
|
||||
.gpio20 = GPIO_MODE_NATIVE,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_NATIVE,
|
||||
.gpio23 = GPIO_MODE_NATIVE,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_NATIVE,
|
||||
.gpio26 = GPIO_MODE_NATIVE,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_GPIO,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_OUTPUT,
|
||||
.gpio8 = GPIO_DIR_INPUT,
|
||||
.gpio11 = GPIO_DIR_OUTPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_INPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio21 = GPIO_DIR_OUTPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio27 = GPIO_DIR_INPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_INPUT,
|
||||
.gpio31 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio7 = GPIO_LEVEL_HIGH,
|
||||
.gpio11 = GPIO_LEVEL_HIGH,
|
||||
.gpio21 = GPIO_LEVEL_HIGH,
|
||||
.gpio24 = GPIO_LEVEL_HIGH,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio0 = GPIO_INVERT,
|
||||
.gpio1 = GPIO_INVERT,
|
||||
.gpio6 = GPIO_INVERT,
|
||||
.gpio8 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
.gpio14 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_GPIO,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_NATIVE,
|
||||
.gpio36 = GPIO_MODE_NATIVE,
|
||||
.gpio37 = GPIO_MODE_NATIVE,
|
||||
.gpio38 = GPIO_MODE_NATIVE,
|
||||
.gpio39 = GPIO_MODE_NATIVE,
|
||||
.gpio40 = GPIO_MODE_NATIVE,
|
||||
.gpio41 = GPIO_MODE_NATIVE,
|
||||
.gpio42 = GPIO_MODE_NATIVE,
|
||||
.gpio43 = GPIO_MODE_NATIVE,
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_GPIO,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_NATIVE,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_NATIVE,
|
||||
.gpio51 = GPIO_MODE_NATIVE,
|
||||
.gpio52 = GPIO_MODE_NATIVE,
|
||||
.gpio53 = GPIO_MODE_NATIVE,
|
||||
.gpio54 = GPIO_MODE_NATIVE,
|
||||
.gpio55 = GPIO_MODE_NATIVE,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE,
|
||||
.gpio60 = GPIO_MODE_NATIVE,
|
||||
.gpio61 = GPIO_MODE_NATIVE,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_OUTPUT,
|
||||
.gpio33 = GPIO_DIR_INPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio46 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_NATIVE,
|
||||
.gpio65 = GPIO_MODE_NATIVE,
|
||||
.gpio66 = GPIO_MODE_NATIVE,
|
||||
.gpio67 = GPIO_MODE_NATIVE,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_NATIVE,
|
||||
.gpio71 = GPIO_MODE_NATIVE,
|
||||
.gpio72 = GPIO_MODE_GPIO,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
};
|
||||
|
||||
static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
.reset = &pch_gpio_set2_reset,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
.reset = &pch_gpio_set3_reset,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* This file is part of the coreboot project. */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {};
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/* This file is part of the coreboot project. */
|
||||
|
||||
#ifndef X9SCL_H
|
||||
#define X9SCL_H
|
||||
|
||||
#define X9SCL_NCT6776_PNP_BASE 0x002e
|
||||
#define X9SCL_NCT6776_HWM_BASE 0x0a30
|
||||
#define X9SCL_NCT6776_GPIO_BASE 0x0a80
|
||||
#define X9SCL_WPCM450_KCS_BASE 0x0ca2
|
||||
#define X9SCL_WPCM450_PNP_BASE 0x164e
|
||||
|
||||
#endif /* X9SCL_H */
|
||||
Loading…
Reference in New Issue