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mb/ibm/sbp1: Disable SIO Uarts 

Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead.

TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC
console. Also made sure coreboot logs are accessible via VUART.

Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Naresh Solanki 2023-07-10 12:43:26 +02:00 committed by Felix Held
parent ce3c77c305
commit 3e52d7955f
2 changed files with 2 additions and 11 deletions
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3
src/mainboard/ibm/sbp1/bootblock.c
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@ -28,7 +28,4 @@ void bootblock_mainboard_early_init(void)
/* Enable com1 (0x3f8) and superio (0x2e) */ /* Enable com1 (0x3f8) and superio (0x2e) */
pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod); pci_write_config16(PCH_DEV_LPC, LPC_IO_DECODE, lpciod);
pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe); pci_write_config16(PCH_DEV_LPC, LPC_IO_ENABLES, lpcioe);
const pnp_devfn_t serial_dev = PNP_DEV(ASPEED_SIO_PORT, AST2400_SUART1);
aspeed_enable_serial(serial_dev, CONFIG_TTYS0_BASE);
} }

10
src/mainboard/ibm/sbp1/devicetree.cb
View File

@ -10,14 +10,8 @@ chip soc/intel/xeon_sp/spr
device pnp 2e.0 on device pnp 2e.0 on
chip superio/aspeed/ast2400 chip superio/aspeed/ast2400
register "use_espi" = "1" register "use_espi" = "1"
device pnp 2e.2 on # SUART1 device pnp 2e.2 off end # SUART1
io 0x60 = 0x3f8 device pnp 2e.3 off end # SUART2
irq 0x70 = 4
end
device pnp 2e.3 on # SUART2
io 0x60 = 0x2f8
irq 0x70 = 3
end
end end
end end
end end