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vendorcode/intel/fsp: Update FSP header for Tiger Lake

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Update FSPM header to include DisableDimmCh Upds for Tiger Lake
platform version 2457.

BUG=b:152000235
BRANCH=none
TEST="Build and Boot on Ripto/Volteer"

Change-Id: Ic743cb2134e6273a63c1212506c81ccbbdec442a
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This commit is contained in:
Ronak Kanabar 2020-03-23 17:17:47 +05:30 committed by Furquan Shaikh
parent 45808399fc
commit 3e666898cd
1 changed files with 38 additions and 6 deletions
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44
src/vendorcode/intel/fsp/fsp2_0/tigerlake/FspmUpd.h
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@ -356,9 +356,41 @@ typedef struct {
**/
UINT8 RMT;
/** Offset 0x0194 - Reserved
/** Offset 0x0194 - DisableDimmCh0
**/
UINT8 Reserved8[10];
UINT8 DisableDimmCh0;
/** Offset 0x0195 - DisableDimmCh1
**/
UINT8 DisableDimmCh1;
/** Offset 0x0196 - DisableDimmCh2
**/
UINT8 DisableDimmCh2;
/** Offset 0x0197 - DisableDimmCh3
**/
UINT8 DisableDimmCh3;
/** Offset 0x0198 - DisableDimmCh4
**/
UINT8 DisableDimmCh4;
/** Offset 0x0199 - DisableDimmCh5
**/
UINT8 DisableDimmCh5;
/** Offset 0x019A - DisableDimmCh6
**/
UINT8 DisableDimmCh6;
/** Offset 0x019B - DisableDimmCh7
**/
UINT8 DisableDimmCh7;
/** Offset 0x019C - Reserved
**/
UINT8 Reserved8[2];
/** Offset 0x019E - Memory Reference Clock
100MHz, 133MHz.
@ -861,7 +893,7 @@ typedef struct {
/** Offset 0x0775 - Reserved
**/
UINT8 Reserved38[355];
UINT8 Reserved38[315];
} FSP_M_CONFIG;
/** Fsp M UPD Configuration
@ -880,11 +912,11 @@ typedef struct {
**/
FSP_M_CONFIG FspmConfig;
/** Offset 0x08D8
/** Offset 0x08B0
**/
UINT8 UnusedUpdSpace24[6];
UINT8 UnusedUpdSpace23[6];
/** Offset 0x08DE
/** Offset 0x08B6
**/
UINT16 UpdTerminator;
} FSPM_UPD;