vendorcode/intel/fsp: Update FSP header for Tiger Lake
Update FSPM header to include DisableDimmCh Upds for Tiger Lake platform version 2457. BUG=b:152000235 BRANCH=none TEST="Build and Boot on Ripto/Volteer" Change-Id: Ic743cb2134e6273a63c1212506c81ccbbdec442a Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39797 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
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@ -356,9 +356,41 @@ typedef struct {
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**/
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**/
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UINT8 RMT;
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UINT8 RMT;
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/** Offset 0x0194 - Reserved
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/** Offset 0x0194 - DisableDimmCh0
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**/
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**/
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UINT8 Reserved8[10];
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UINT8 DisableDimmCh0;
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/** Offset 0x0195 - DisableDimmCh1
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**/
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UINT8 DisableDimmCh1;
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/** Offset 0x0196 - DisableDimmCh2
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**/
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UINT8 DisableDimmCh2;
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/** Offset 0x0197 - DisableDimmCh3
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**/
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UINT8 DisableDimmCh3;
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/** Offset 0x0198 - DisableDimmCh4
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**/
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UINT8 DisableDimmCh4;
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/** Offset 0x0199 - DisableDimmCh5
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**/
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UINT8 DisableDimmCh5;
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/** Offset 0x019A - DisableDimmCh6
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**/
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UINT8 DisableDimmCh6;
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/** Offset 0x019B - DisableDimmCh7
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**/
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UINT8 DisableDimmCh7;
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/** Offset 0x019C - Reserved
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**/
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UINT8 Reserved8[2];
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/** Offset 0x019E - Memory Reference Clock
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/** Offset 0x019E - Memory Reference Clock
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100MHz, 133MHz.
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100MHz, 133MHz.
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@ -861,7 +893,7 @@ typedef struct {
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/** Offset 0x0775 - Reserved
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/** Offset 0x0775 - Reserved
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**/
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**/
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UINT8 Reserved38[355];
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UINT8 Reserved38[315];
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} FSP_M_CONFIG;
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} FSP_M_CONFIG;
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/** Fsp M UPD Configuration
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/** Fsp M UPD Configuration
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@ -880,11 +912,11 @@ typedef struct {
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**/
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**/
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FSP_M_CONFIG FspmConfig;
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FSP_M_CONFIG FspmConfig;
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/** Offset 0x08D8
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/** Offset 0x08B0
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**/
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**/
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UINT8 UnusedUpdSpace24[6];
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UINT8 UnusedUpdSpace23[6];
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/** Offset 0x08DE
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/** Offset 0x08B6
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**/
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**/
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UINT16 UpdTerminator;
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UINT16 UpdTerminator;
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} FSPM_UPD;
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} FSPM_UPD;
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