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amd southbirdge sb800 wrapper, pci bridge fix 

sb800 pci bridge SHOULD enabled by default according to the chipset document,
but actually not enabled on some mainboard.
enable sb800 pci bridge when told to enable in devicetree.cb.
tested on ibase persimmon mainboard.

Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/63
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Kerry She 2011-06-24 22:52:15 +08:00 committed by Stefan Reinauer
parent 770b877796
commit 3e706b63c0
5 changed files with 20 additions and 5 deletions
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2
src/mainboard/advansus/a785e-i/devicetree.cb
View File

@ -98,7 +98,7 @@ chip northbridge/amd/amdfam10/root_complex
end
end #superio/winbond/w83627hf
end # LPC 0x439d
device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO.
device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 14.6 off end # Gec
device pci 15.0 on end # PCIe 0

2
src/mainboard/amd/inagua/devicetree.cb
View File

@ -65,7 +65,7 @@ chip northbridge/amd/agesa/family14/root_complex
end
end # kbc1100
end #LPC
device pci 14.4 on end # PCI 0x4384
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 on end # PCIe PortA
device pci 15.1 on end # PCIe PortB

2
src/mainboard/amd/persimmon/devicetree.cb
View File

@ -81,7 +81,7 @@ chip northbridge/amd/agesa/family14/root_complex
end
end # f81865f
end #LPC
device pci 14.4 on end # PCI 0x4384
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 off end # PCIe PortA
device pci 15.1 off end # PCIe PortB

2
src/mainboard/asrock/e350m1/devicetree.cb
View File

@ -97,7 +97,7 @@ chip northbridge/amd/agesa/family14/root_complex
end
end
end #LPC
device pci 14.4 on end # PCI 0x4384
device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0}
device pci 14.5 on end # USB 2
device pci 15.0 on end # PCIe PortA
device pci 15.1 on end # PCIe PortB: NIC

17
src/southbridge/amd/cimx/sb800/late.c
View File

@ -248,6 +248,21 @@ static const struct pci_driver gec_driver __pci_driver = {
.device = PCI_DEVICE_ID_ATI_SB800_GEC,
};
/**
* @brief Enable PCI Bridge
*
* PcibConfig [PM_Reg: EAh], PCIDisable [Bit0]
* 'PCIDisable' set to 0 to enable P2P bridge.
* 'PCIDisable' set to 1 to disable P2P bridge and enable PCI interface pins
* to function as GPIO {GPIO 35:0}.
*/
static void pci_init(device_t dev)
{
/* PCI Bridge SHOULD be enabled by default according to SB800 rrg,
* but actually was disabled in some platform, so I have to enabled it.
*/
RWMEM(ACPI_MMIO_BASE + PMIO_BASE + SB_PMIOA_REGEA, AccWidthUint8, ~BIT0, 0);
}
static void pcie_init(device_t dev)
{
@ -258,7 +273,7 @@ static struct device_operations pci_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pcie_init,
.init = pci_init,
.scan_bus = pci_scan_bridge,
.reset_bus = pci_bus_reset,
.ops_pci = &lops_pci,