mb/intel/baskingridge: Factor out common MRC settings
There's no need to redefine common settings. Change-Id: If0cbc147791496bafc85831c1f88d3eb71b63350 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
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Angel Pons
parent
e8ecabca73
commit
3e72f87fe7
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@ -46,70 +46,64 @@ void mainboard_config_rcba(void)
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void mainboard_fill_pei_data(struct pei_data *pei_data)
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{
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struct pei_data mainboard_pei_data = {
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.pei_version = PEI_VERSION,
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.mchbar = (uintptr_t)DEFAULT_MCHBAR,
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.dmibar = (uintptr_t)DEFAULT_DMIBAR,
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.epbar = DEFAULT_EPBAR,
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.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
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.smbusbar = SMBUS_IO_BASE,
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.hpet_address = HPET_ADDR,
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.rcba = (uintptr_t)DEFAULT_RCBA,
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.pmbase = DEFAULT_PMBASE,
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.gpiobase = DEFAULT_GPIOBASE,
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.temp_mmio_base = 0xfed08000,
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.system_type = 0, // 0 Mobile, 1 Desktop/Server
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.tseg_size = CONFIG_SMM_TSEG_SIZE,
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.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 },
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.ec_present = 0,
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// 0 = leave channel enabled
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// 1 = disable dimm 0 on channel
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// 2 = disable dimm 1 on channel
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// 3 = disable dimm 0+1 on channel
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.dimm_channel0_disabled = 0,
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.dimm_channel1_disabled = 0,
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.max_ddr3_freq = 1600,
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.usb2_ports = {
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/* Length, Enable, OCn#, Location */
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{ 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */
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USB_PORT_FLEX },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */
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USB_PORT_DOCK },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */
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USB_PORT_MINI_PCIE },
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{ 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */
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USB_PORT_FLEX },
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{ 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
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USB_PORT_FRONT_PANEL },
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},
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.usb3_ports = {
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/* Enable, OCn# */
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{ 1, 0 }, /* P1; */
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{ 1, 0 }, /* P2; */
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{ 1, 0 }, /* P3; */
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{ 1, 0 }, /* P4; */
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{ 1, 0 }, /* P6; */
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{ 1, 0 }, /* P6; */
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},
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pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */
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pei_data->spd_addresses[0] = 0xa0;
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pei_data->spd_addresses[1] = 0xa2;
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pei_data->spd_addresses[2] = 0xa4;
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pei_data->spd_addresses[3] = 0xa6;
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pei_data->ec_present = 0;
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/*
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* 0 = leave channel enabled
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* 1 = disable dimm 0 on channel
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* 2 = disable dimm 1 on channel
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* 3 = disable dimm 0+1 on channel
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*/
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pei_data->dimm_channel0_disabled = 0;
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pei_data->dimm_channel1_disabled = 0;
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pei_data->max_ddr3_freq = 1600;
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struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
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/* Length, Enable, OCn#, Location */
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{ 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, 0, /* P1: Back USB3 port (OC0) */
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USB_PORT_BACK_PANEL },
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{ 0x0040, 1, 1, /* P2: Flex Port on bottom (OC1) */
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USB_PORT_FLEX },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P3: Dock connector */
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USB_PORT_DOCK },
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{ 0x0040, 1, USB_OC_PIN_SKIP, /* P4: Mini PCIE */
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USB_PORT_MINI_PCIE },
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{ 0x0040, 1, 1, /* P5: USB eSATA header (OC1) */
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USB_PORT_FLEX },
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{ 0x0040, 1, 3, /* P6: Front Header J8H2 (OC3) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 3, /* P7: Front Header J8H2 (OC3) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 4, /* P8: USB/LAN Jack (OC4) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 4, /* P9: USB/LAN Jack (OC4) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 5, /* P10: Front Header J7H3 (OC5) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 5, /* P11: Front Header J7H3 (OC5) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 6, /* P12: USB/DP Jack (OC6) */
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USB_PORT_FRONT_PANEL },
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{ 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
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USB_PORT_FRONT_PANEL },
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};
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*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */
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struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
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/* Enable, OCn# */
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{ 1, 0 }, /* P1; */
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{ 1, 0 }, /* P2; */
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{ 1, 0 }, /* P3; */
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{ 1, 0 }, /* P4; */
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{ 1, 0 }, /* P6; */
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{ 1, 0 }, /* P6; */
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};
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memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
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memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
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}
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