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mb/intel/baskingridge: Factor out common MRC settings 

There's no need to redefine common settings.

Change-Id: If0cbc147791496bafc85831c1f88d3eb71b63350
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This commit is contained in:
Angel Pons 2020-07-03 18:33:56 +02:00
parent e8ecabca73
commit 3e72f87fe7
1 changed files with 58 additions and 64 deletions
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50
src/mainboard/intel/baskingridge/romstage.c
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@ -46,30 +46,23 @@ void mainboard_config_rcba(void)
void mainboard_fill_pei_data(struct pei_data *pei_data) void mainboard_fill_pei_data(struct pei_data *pei_data)
{ {
struct pei_data mainboard_pei_data = { pei_data->system_type = 0; /* 0 Mobile, 1 Desktop/Server */
.pei_version = PEI_VERSION, pei_data->spd_addresses[0] = 0xa0;
.mchbar = (uintptr_t)DEFAULT_MCHBAR, pei_data->spd_addresses[1] = 0xa2;
.dmibar = (uintptr_t)DEFAULT_DMIBAR, pei_data->spd_addresses[2] = 0xa4;
.epbar = DEFAULT_EPBAR, pei_data->spd_addresses[3] = 0xa6;
.pciexbar = CONFIG_MMCONF_BASE_ADDRESS, pei_data->ec_present = 0;
.smbusbar = SMBUS_IO_BASE, /*
.hpet_address = HPET_ADDR, * 0 = leave channel enabled
.rcba = (uintptr_t)DEFAULT_RCBA, * 1 = disable dimm 0 on channel
.pmbase = DEFAULT_PMBASE, * 2 = disable dimm 1 on channel
.gpiobase = DEFAULT_GPIOBASE, * 3 = disable dimm 0+1 on channel
.temp_mmio_base = 0xfed08000, */
.system_type = 0, // 0 Mobile, 1 Desktop/Server pei_data->dimm_channel0_disabled = 0;
.tseg_size = CONFIG_SMM_TSEG_SIZE, pei_data->dimm_channel1_disabled = 0;
.spd_addresses = { 0xa0, 0xa2, 0xa4, 0xa6 }, pei_data->max_ddr3_freq = 1600;
.ec_present = 0,
// 0 = leave channel enabled struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
// 1 = disable dimm 0 on channel
// 2 = disable dimm 1 on channel
// 3 = disable dimm 0+1 on channel
.dimm_channel0_disabled = 0,
.dimm_channel1_disabled = 0,
.max_ddr3_freq = 1600,
.usb2_ports = {
/* Length, Enable, OCn#, Location */ /* Length, Enable, OCn#, Location */
{ 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */ { 0x0040, 1, 0, /* P0: Back USB3 port (OC0) */
USB_PORT_BACK_PANEL }, USB_PORT_BACK_PANEL },
@ -99,8 +92,9 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
USB_PORT_FRONT_PANEL }, USB_PORT_FRONT_PANEL },
{ 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */ { 0x0040, 1, 6, /* P13: USB/DP Jack (OC6) */
USB_PORT_FRONT_PANEL }, USB_PORT_FRONT_PANEL },
}, };
.usb3_ports = {
struct usb3_port_setting usb3_ports[MAX_USB3_PORTS] = {
/* Enable, OCn# */ /* Enable, OCn# */
{ 1, 0 }, /* P1; */ { 1, 0 }, /* P1; */
{ 1, 0 }, /* P2; */ { 1, 0 }, /* P2; */
@ -108,8 +102,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
{ 1, 0 }, /* P4; */ { 1, 0 }, /* P4; */
{ 1, 0 }, /* P6; */ { 1, 0 }, /* P6; */
{ 1, 0 }, /* P6; */ { 1, 0 }, /* P6; */
},
}; };
*pei_data = mainboard_pei_data; /* FIXME: Do not overwrite everything */ memcpy(pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports));
memcpy(pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports));
} }