soc/intel: Drop pmc_soc_restore_power_failure()

Get rid of this function and its dangerous, weak implementation.
Instead, call pmc_set_power_failure_state() directly from the SMI
handler.

Change-Id: I0718afc5db66447c93289643f9097a4257b10934
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nico Huber 2019-08-05 21:12:33 +02:00
parent 2fe596e677
commit 3e786b5546
7 changed files with 2 additions and 39 deletions

View File

@ -105,11 +105,6 @@ void pmc_soc_set_afterg3_en(const bool on)
write32(gen_pmcon1, reg32);
}
void pmc_soc_restore_power_failure(void)
{
pmc_set_power_failure_state(false);
}
void pmc_soc_init(struct device *dev)
{
const struct soc_intel_apollolake_config *cfg = config_of(dev);

View File

@ -45,11 +45,6 @@ void pmc_soc_set_afterg3_en(const bool on)
write8(pmcbase + GEN_PMCON_A, reg8);
}
void pmc_soc_restore_power_failure(void)
{
pmc_set_power_failure_state(false);
}
static void pm1_enable_pwrbtn_smi(void *unused)
{
/*

View File

@ -126,12 +126,6 @@ void pmc_clear_all_gpe_status(void);
/* Clear status bits in Power and Reset Status (PRSTS) register */
void pmc_clear_prsts(void);
/*
* Set PMC register to know which state system should be after
* power reapplied
*/
void pmc_soc_restore_power_failure(void);
/*
* Enable or disable global reset. If global reset is enabled, hard reset and
* soft reset will trigger global reset, where both host and TXE are reset.

View File

@ -79,18 +79,6 @@ __weak uint32_t soc_get_smi_status(uint32_t generic_sts)
return generic_sts;
}
/*
* Set PMC register to know which state system should be after
* power reapplied
*/
__weak void pmc_soc_restore_power_failure(void)
{
/*
* SoC code should set PMC config register in order to set
* MAINBOARD_POWER_ON bit as per EDS.
*/
}
int acpi_get_sleep_type(void)
{
struct chipset_power_state *ps;

View File

@ -29,6 +29,7 @@
#include <intelblocks/uart.h>
#include <smmstore.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
#include <soc/pm.h>
#include <soc/gpio.h>
#include <soc/iomap.h>
@ -221,7 +222,7 @@ void smihandler_southbridge_sleep(
/* Disable all GPE */
pmc_disable_all_gpe();
/* Set which state system will be after power reapplied */
pmc_soc_restore_power_failure();
pmc_set_power_failure_state(false);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);

View File

@ -42,11 +42,6 @@ void pmc_soc_set_afterg3_en(const bool on)
write8(pmcbase + GEN_PMCON_A, reg8);
}
void pmc_soc_restore_power_failure(void)
{
pmc_set_power_failure_state(false);
}
static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable)
{
uint32_t reg;

View File

@ -68,11 +68,6 @@ void pmc_soc_set_afterg3_en(const bool on)
pci_write_config8(dev, GEN_PMCON_B, reg8);
}
void pmc_soc_restore_power_failure(void)
{
pmc_set_power_failure_state(false);
}
#if ENV_RAMSTAGE
/* Fill up PMC resource structure */
int pmc_soc_get_resources(struct pmc_resource_config *cfg)