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src: Drop useless cache flush settings in FADT 

They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.

Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.

Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This commit is contained in:
Angel Pons 2020-07-13 01:41:00 +02:00
parent b74975e403
commit 3eb8dbaee2
21 changed files with 0 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/picasso/acpi.c
View File

@ -110,8 +110,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = 0; /* 0x7d these have to be */

2
src/soc/amd/stoneyridge/acpi.c
View File

@ -82,8 +82,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = 0; /* 0x7d these have to be */

2
src/soc/intel/baytrail/fadt.c
View File

@ -32,8 +32,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;

2
src/soc/intel/braswell/fadt.c
View File

@ -32,8 +32,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 2 * (GPE0_EN - GPE0_STS);
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;

2
src/soc/intel/broadwell/fadt.c
View File

@ -31,8 +31,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 32;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;

2
src/soc/intel/common/block/acpi/acpi.c
View File

@ -114,8 +114,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
/* GPE0 STS/EN pairs each 32 bits wide. */
fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
fadt->flush_size = 0x400; /* twice of cache size */
fadt->flush_stride = 0x10; /* Cache line width */
fadt->duty_offset = 1;
fadt->day_alrm = 0xd;

2
src/soc/intel/denverton_ns/acpi.c
View File

@ -129,8 +129,6 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1;
fadt->duty_width = 0;

2
src/soc/intel/skylake/fadt.c
View File

@ -35,8 +35,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;

2
src/soc/intel/xeon_sp/cpx/acpi.c
View File

@ -293,8 +293,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
/* GPE0 STS/EN pairs each 32 bits wide. */
fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
fadt->flush_size = 0x400; /* twice of cache size */
fadt->flush_stride = 0x10; /* Cache line width */
fadt->duty_offset = 1;
fadt->day_alrm = 0xd;

2
src/soc/intel/xeon_sp/skx/acpi.c
View File

@ -252,8 +252,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t);
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1;
fadt->duty_width = 0;

2
src/southbridge/amd/agesa/hudson/fadt.c
View File

@ -46,8 +46,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = 0; /* 0x7d these have to be */

2
src/southbridge/amd/cimx/sb800/fadt.c
View File

@ -72,8 +72,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = 0; /* 0x7d these have to be */

2
src/southbridge/amd/pi/hudson/fadt.c
View File

@ -46,8 +46,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED;
fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED;
fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */
fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */
fadt->duty_width = 3; /* CLK_VAL bits 3:1 */
fadt->day_alrm = 0; /* 0x7d these have to be */

3
src/southbridge/intel/bd82x6x/fadt.c
View File

@ -39,9 +39,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
}
fadt->p_lvl2_lat = c2_latency;
fadt->p_lvl3_lat = 87;
/* flush_* is ignored if ACPI_FADT_WBINVD is set */
fadt->flush_size = 0;
fadt->flush_stride = 0;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;

2
src/southbridge/intel/i82371eb/fadt.c
View File

@ -38,8 +38,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl2_lat = 101; /* >100 means c2 not supported */
fadt->p_lvl3_lat = 1001; /* >1000 means c3 not supported */
fadt->flush_size = 0; /* only needed if CPU wbinvd is broken */
fadt->flush_stride = 0;
fadt->duty_offset = 1; /* bit 1:3 in PCNTRL reg (pmbase+0x10) */
fadt->duty_width = 3; /* this width is in bits */
fadt->day_alrm = 0x0d; /* rtc CMOS RAM offset */

2
src/southbridge/intel/i82801dx/fadt.c
View File

@ -41,8 +41,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 8;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 85;
fadt->flush_size = 1024;
fadt->flush_stride = 16;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;

2
src/southbridge/intel/i82801gx/fadt.c
View File

@ -38,8 +38,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 8;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = chip->c3_latency;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
if (chip->p_cnt_throttling_supported)
fadt->duty_width = 3;

2
src/southbridge/intel/i82801ix/fadt.c
View File

@ -34,8 +34,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 16;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 0x39;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 3;
fadt->day_alrm = 0xd;

2
src/southbridge/intel/i82801jx/fadt.c
View File

@ -37,8 +37,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->gpe0_blk_len = 16;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = chip->c3_latency;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 1;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;

3
src/southbridge/intel/ibexpeak/fadt.c
View File

@ -39,9 +39,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
}
fadt->p_lvl2_lat = c2_latency;
fadt->p_lvl3_lat = 87;
/* flush_* is ignored if ACPI_FADT_WBINVD is set */
fadt->flush_size = 0;
fadt->flush_stride = 0;
/* P_CNT not supported */
fadt->duty_offset = 0;
fadt->duty_width = 0;

2
src/southbridge/intel/lynxpoint/fadt.c
View File

@ -46,8 +46,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 0;
fadt->flush_stride = 0;
fadt->duty_offset = 0;
fadt->duty_width = 0;
fadt->day_alrm = 0xd;