GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/amd/picasso: Add UPDs for support eDP power sequence adjust 

Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.

BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Chris Wang 2020-12-23 04:29:57 +08:00 committed by Patrick Georgi
parent 27b149c30b
commit 3ec3cb82f9
2 changed files with 25 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/soc/amd/picasso/chip.h
View File

@ -243,6 +243,20 @@ struct soc_amd_picasso_config {
uint8_t boostadj; uint8_t boostadj;
uint16_t margin_deemph; uint16_t margin_deemph;
} edp_tuningset; } edp_tuningset;
/*
* eDP panel power sequence control
* all pwr sequence numbers below are in uint of 4ms and "0" as default value
*/
uint8_t edp_pwr_adjust_enable;
uint8_t pwron_digon_to_de;
uint8_t pwron_de_to_varybl;
uint8_t pwrdown_varybloff_to_de;
uint8_t pwrdown_de_to_digoff;
uint8_t pwroff_delay;
uint8_t pwron_varybl_to_blon;
uint8_t pwrdown_bloff_to_varybloff;
uint8_t min_allowed_bl_level;
}; };
#endif /* __PICASSO_CHIP_H__ */ #endif /* __PICASSO_CHIP_H__ */

11
src/soc/amd/picasso/fsp_params.c
View File

@ -152,6 +152,17 @@ static void fsp_edp_tuning_upds(FSP_S_CONFIG *scfg,
scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4; scfg->Deemph6db4 = cfg->edp_tuningset.deemph_6db4;
scfg->BoostAdj = cfg->edp_tuningset.boostadj; scfg->BoostAdj = cfg->edp_tuningset.boostadj;
} }
if (cfg->edp_pwr_adjust_enable) {
scfg->pwron_digon_to_de = cfg->pwron_digon_to_de;
scfg->pwron_de_to_varybl = cfg->pwron_de_to_varybl;
scfg->pwrdown_varybloff_to_de = cfg->pwrdown_varybloff_to_de;
scfg->pwrdown_de_to_digoff = cfg->pwrdown_de_to_digoff;
scfg->pwroff_delay = cfg->pwroff_delay;
scfg->pwron_varybl_to_blon = cfg->pwron_varybl_to_blon;
scfg->pwrdown_bloff_to_varybloff = cfg->pwrdown_bloff_to_varybloff;
scfg->min_allowed_bl_level = cfg->min_allowed_bl_level;
}
} }
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)