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mb/asus/h61-series: Consolidate devicetree SATA options 

The H61 PCH only supports 4 SATA ports, and does not support Gen3.

Change-Id: I3e060ca6904fd6c773c322988a17bbca28333a3d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Angel Pons 2021-05-17 14:04:33 +02:00 committed by Patrick Georgi
parent 270ce521de
commit 3ec960a482
2 changed files with 1 additions and 2 deletions
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2
src/mainboard/asus/h61-series/variants/p8h61-m_lx3_r2_0/devicetree.cb
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@ -19,7 +19,7 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x chip southbridge/intel/bd82x6x
register "c2_latency" = "0x0065" register "c2_latency" = "0x0065"
register "gen1_dec" = "0x000c0291" register "gen1_dec" = "0x000c0291"
register "sata_port_map" = "0x3f" register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"

1
src/mainboard/asus/h61-series/variants/p8h61-m_pro/devicetree.cb
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@ -18,7 +18,6 @@ chip northbridge/intel/sandybridge
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
register "c2_latency" = "0x0065" register "c2_latency" = "0x0065"
register "gen1_dec" = "0x000c0291" # HWM register "gen1_dec" = "0x000c0291" # HWM
register "sata_interface_speed_support" = "0x3"
register "sata_port_map" = "0x33" register "sata_port_map" = "0x33"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"